A 3Gb/s/ch Transceiver for RC-limited On-Chip Interconnects

Daniel Schinkel, E. Mensink, Eric A.M. Klumperink, Adrianus Johannes Maria van Tuijl, Bram Nauta

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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    Abstract

    A bus-transceiver chip in 0.13 μm CMOS uses 10mm uninterrupted differential interconnects of 0.8 μm pitch (82MHz RC-limited bandwidth). The chip achieves 3Gb/s/ch using a pulse-width pre-emphasis technique in combination with resistive termination while twisted interconnects mitigate crosstalk. Power consumption is 6mW/ch at a 1.2V supply.
    Original languageEnglish
    Title of host publicationIEEE International Solid-State Circuits Conference 2005 (ISSCC 2005)
    Place of PublicationSan Francisco
    PublisherIEEE
    Pages386-387+605
    Number of pages3
    ISBN (Print)0780389042
    DOIs
    Publication statusPublished - Feb 2005
    EventIEEE International Solid-State Circuits Conference, ISSCC 2005 - San Francisco, United States
    Duration: 6 Feb 200510 Feb 2005

    Publication series

    Name
    PublisherIEEE
    Volume1

    Conference

    ConferenceIEEE International Solid-State Circuits Conference, ISSCC 2005
    Abbreviated titleISSCC
    CountryUnited States
    CitySan Francisco
    Period6/02/0510/02/05

    Keywords

    • METIS-224170
    • EWI-14509
    • IR-52558

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