A 3Gb/s/ch Transceiver for RC-limited On-Chip Interconnects

Daniel Schinkel; E. Mensink; Eric A.M. Klumperink; Adrianus Johannes Maria van Tuijl; Bram Nauta

doi:10.1109/ISSCC.2005.1494031

A 3Gb/s/ch Transceiver for RC-limited On-Chip Interconnects

Daniel Schinkel, E. Mensink, Eric A.M. Klumperink, Adrianus Johannes Maria van Tuijl, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

A bus-transceiver chip in 0.13 μm CMOS uses 10mm uninterrupted differential interconnects of 0.8 μm pitch (82MHz RC-limited bandwidth). The chip achieves 3Gb/s/ch using a pulse-width pre-emphasis technique in combination with resistive termination while twisted interconnects mitigate crosstalk. Power consumption is 6mW/ch at a 1.2V supply.

Original language	English
Title of host publication	IEEE International Solid-State Circuits Conference 2005 (ISSCC 2005)
Place of Publication	San Francisco
Publisher	IEEE
Pages	386-387+605
Number of pages	3
ISBN (Print)	0780389042
DOIs	https://doi.org/10.1109/ISSCC.2005.1494031
Publication status	Published - Feb 2005
Event	IEEE International Solid-State Circuits Conference, ISSCC 2005 - San Francisco, United States Duration: 6 Feb 2005 → 10 Feb 2005

Publication series

Name
Publisher	IEEE
Volume	1

Conference

Conference	IEEE International Solid-State Circuits Conference, ISSCC 2005
Abbreviated title	ISSCC
Country/Territory	United States
City	San Francisco
Period	6/02/05 → 10/02/05

Keywords

METIS-224170
EWI-14509
IR-52558

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10.1109/ISSCC.2005.1494031

01494031Final published version, 3.06 MB

Cite this

@inproceedings{e5234928ca2a4f54b6441c882021e204,

title = "A 3Gb/s/ch Transceiver for RC-limited On-Chip Interconnects",

abstract = "A bus-transceiver chip in 0.13 μm CMOS uses 10mm uninterrupted differential interconnects of 0.8 μm pitch (82MHz RC-limited bandwidth). The chip achieves 3Gb/s/ch using a pulse-width pre-emphasis technique in combination with resistive termination while twisted interconnects mitigate crosstalk. Power consumption is 6mW/ch at a 1.2V supply.",

keywords = "METIS-224170, EWI-14509, IR-52558",

author = "Daniel Schinkel and E. Mensink and Klumperink, {Eric A.M.} and {van Tuijl}, {Adrianus Johannes Maria} and Bram Nauta",

year = "2005",

month = feb,

doi = "10.1109/ISSCC.2005.1494031",

language = "English",

isbn = "0780389042",

publisher = "IEEE",

pages = "386--387+605",

booktitle = "IEEE International Solid-State Circuits Conference 2005 (ISSCC 2005)",

address = "United States",

note = "IEEE International Solid-State Circuits Conference, ISSCC 2005, ISSCC ; Conference date: 06-02-2005 Through 10-02-2005",

}

Schinkel, D, Mensink, E, Klumperink, EAM, van Tuijl, AJM & Nauta, B 2005, A 3Gb/s/ch Transceiver for RC-limited On-Chip Interconnects. in IEEE International Solid-State Circuits Conference 2005 (ISSCC 2005). IEEE, San Francisco, pp. 386-387+605, IEEE International Solid-State Circuits Conference, ISSCC 2005, San Francisco, United States, 6/02/05. https://doi.org/10.1109/ISSCC.2005.1494031

TY - GEN

T1 - A 3Gb/s/ch Transceiver for RC-limited On-Chip Interconnects

AU - Schinkel, Daniel

AU - Mensink, E.

AU - Klumperink, Eric A.M.

AU - van Tuijl, Adrianus Johannes Maria

AU - Nauta, Bram

PY - 2005/2

Y1 - 2005/2

N2 - A bus-transceiver chip in 0.13 μm CMOS uses 10mm uninterrupted differential interconnects of 0.8 μm pitch (82MHz RC-limited bandwidth). The chip achieves 3Gb/s/ch using a pulse-width pre-emphasis technique in combination with resistive termination while twisted interconnects mitigate crosstalk. Power consumption is 6mW/ch at a 1.2V supply.

AB - A bus-transceiver chip in 0.13 μm CMOS uses 10mm uninterrupted differential interconnects of 0.8 μm pitch (82MHz RC-limited bandwidth). The chip achieves 3Gb/s/ch using a pulse-width pre-emphasis technique in combination with resistive termination while twisted interconnects mitigate crosstalk. Power consumption is 6mW/ch at a 1.2V supply.

KW - METIS-224170

KW - EWI-14509

KW - IR-52558

U2 - 10.1109/ISSCC.2005.1494031

DO - 10.1109/ISSCC.2005.1494031

M3 - Conference contribution

SN - 0780389042

SP - 386-387+605

BT - IEEE International Solid-State Circuits Conference 2005 (ISSCC 2005)

PB - IEEE

CY - San Francisco

T2 - IEEE International Solid-State Circuits Conference, ISSCC 2005

Y2 - 6 February 2005 through 10 February 2005

ER -

A 3Gb/s/ch Transceiver for RC-limited On-Chip Interconnects

Abstract

Publication series

Conference

Keywords

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