A bus-transceiver chip in 0.13 μm CMOS uses 10mm uninterrupted differential interconnects of 0.8 μm pitch (82MHz RC-limited bandwidth). The chip achieves 3Gb/s/ch using a pulse-width pre-emphasis technique in combination with resistive termination while twisted interconnects mitigate crosstalk. Power consumption is 6mW/ch at a 1.2V supply.
|Conference||IEEE International Solid-State Circuits Conference, ISSCC 2005|
|Period||6/02/05 → 10/02/05|