A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply

Harijot Singh Bindra; Anne J. Annema; Gerhardus J.M. Wienk; Bram  Nauta; Simon Louwsma

doi:10.1109/CICC.2019.8780150

A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply

Harijot Singh Bindra, Anne J. Annema, Gerhardus J.M. Wienk, Bram Nauta, Simon Louwsma

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

23 Citations (Scopus)

551 Downloads (Pure)

Abstract

We present a 10b differential SAR ADC integrated with unity gain (Class-A) voltage buffers, operating from a single supply voltage 1.2V and handling near rail-to-rail inputs. The two differential inputs are first compared and depending on the comparison result, the inputs are either swapped or not, after which these signals are buffered, sampled and converted. This way each of the two buffers needs to handle only half of the full-scale range which enables operation of the Class-A buffers at the ADC supply voltage while providing an overall near rail-to-rail (full-scale) input range for conversion. The buffered ADC can handle 2V _P-P differential input and consumes 149μW at 4MS/s to achieve a state-of-the-art Walden FoM of 87fJ/conversion-step including buffers. The buffered ADC was designed in a 65nm CMOS process and occupies an active area of 0.04mm ².

Original language	English
Title of host publication	2019 IEEE Custom Integrated Circuits Conference (CICC)
Place of Publication	Austin, TX, USA
Publisher	IEEE
ISBN (Electronic)	978-1-5386-9395-7
DOIs	https://doi.org/10.1109/CICC.2019.8780150
Publication status	Published - 17 Apr 2019
Event	IEEE Custom Integrated Circuits Conference 2019 - Austin, United States Duration: 14 Apr 2019 → 17 Apr 2019

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
Volume	2019-April
ISSN (Print)	0886-5930

Conference

Conference	IEEE Custom Integrated Circuits Conference 2019
Abbreviated title	CICC 2019
Country/Territory	United States
City	Austin
Period	14/04/19 → 17/04/19

Keywords

SAR ADC
input buffer
Class-A driver
nyquist sampling
SFDR
INL
DNL

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10.1109/CICC.2019.8780150

CICC_FinalSubmission_2019Accepted author version, 761 KB

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Bindra, H. S., Annema, A. J., Wienk, G. J. M., Nauta, B., & Louwsma, S. (2019). A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply. In 2019 IEEE Custom Integrated Circuits Conference (CICC) Article 8780150 (Proceedings of the Custom Integrated Circuits Conference; Vol. 2019-April). IEEE. https://doi.org/10.1109/CICC.2019.8780150

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title = "A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply",

abstract = "We present a 10b differential SAR ADC integrated with unity gain (Class-A) voltage buffers, operating from a single supply voltage 1.2V and handling near rail-to-rail inputs. The two differential inputs are first compared and depending on the comparison result, the inputs are either swapped or not, after which these signals are buffered, sampled and converted. This way each of the two buffers needs to handle only half of the full-scale range which enables operation of the Class-A buffers at the ADC supply voltage while providing an overall near rail-to-rail (full-scale) input range for conversion. The buffered ADC can handle 2V P-P differential input and consumes 149μW at 4MS/s to achieve a state-of-the-art Walden FoM of 87fJ/conversion-step including buffers. The buffered ADC was designed in a 65nm CMOS process and occupies an active area of 0.04mm 2. ",

keywords = "SAR ADC, input buffer, Class-A driver, nyquist sampling, SFDR, INL, DNL",

author = "Bindra, {Harijot Singh} and Annema, {Anne J.} and Wienk, {Gerhardus J.M.} and Bram Nauta and Simon Louwsma",

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doi = "10.1109/CICC.2019.8780150",

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Bindra, HS , Annema, AJ, Wienk, GJM, Nauta, B & Louwsma, S 2019, A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply. in 2019 IEEE Custom Integrated Circuits Conference (CICC) ., 8780150, Proceedings of the Custom Integrated Circuits Conference, vol. 2019-April, IEEE, Austin, TX, USA, IEEE Custom Integrated Circuits Conference 2019 , Austin, Texas, United States, 14/04/19. https://doi.org/10.1109/CICC.2019.8780150

A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply. / Bindra, Harijot Singh ; Annema, Anne J.; Wienk, Gerhardus J.M. et al.
2019 IEEE Custom Integrated Circuits Conference (CICC) . Austin, TX, USA: IEEE, 2019. 8780150 (Proceedings of the Custom Integrated Circuits Conference; Vol. 2019-April).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - Louwsma, Simon

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N2 - We present a 10b differential SAR ADC integrated with unity gain (Class-A) voltage buffers, operating from a single supply voltage 1.2V and handling near rail-to-rail inputs. The two differential inputs are first compared and depending on the comparison result, the inputs are either swapped or not, after which these signals are buffered, sampled and converted. This way each of the two buffers needs to handle only half of the full-scale range which enables operation of the Class-A buffers at the ADC supply voltage while providing an overall near rail-to-rail (full-scale) input range for conversion. The buffered ADC can handle 2V P-P differential input and consumes 149μW at 4MS/s to achieve a state-of-the-art Walden FoM of 87fJ/conversion-step including buffers. The buffered ADC was designed in a 65nm CMOS process and occupies an active area of 0.04mm 2.

AB - We present a 10b differential SAR ADC integrated with unity gain (Class-A) voltage buffers, operating from a single supply voltage 1.2V and handling near rail-to-rail inputs. The two differential inputs are first compared and depending on the comparison result, the inputs are either swapped or not, after which these signals are buffered, sampled and converted. This way each of the two buffers needs to handle only half of the full-scale range which enables operation of the Class-A buffers at the ADC supply voltage while providing an overall near rail-to-rail (full-scale) input range for conversion. The buffered ADC can handle 2V P-P differential input and consumes 149μW at 4MS/s to achieve a state-of-the-art Walden FoM of 87fJ/conversion-step including buffers. The buffered ADC was designed in a 65nm CMOS process and occupies an active area of 0.04mm 2.

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ER -

A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply

Abstract

Publication series

Conference

Keywords

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