Abstract
We present a 10b differential SAR ADC integrated with unity gain (Class-A) voltage buffers, operating from a single supply voltage 1.2V and handling near rail-to-rail inputs. The two differential inputs are first compared and depending on the comparison result, the inputs are either swapped or not, after which these signals are buffered, sampled and converted. This way each of the two buffers needs to handle only half of the full-scale range which enables operation of the Class-A buffers at the ADC supply voltage while providing an overall near rail-to-rail (full-scale) input range for conversion. The buffered ADC can handle 2V P-P differential input and consumes 149μW at 4MS/s to achieve a state-of-the-art Walden FoM of 87fJ/conversion-step including buffers. The buffered ADC was designed in a 65nm CMOS process and occupies an active area of 0.04mm 2.
| Original language | English |
|---|---|
| Title of host publication | 2019 IEEE Custom Integrated Circuits Conference (CICC) |
| Place of Publication | Austin, TX, USA |
| Publisher | IEEE |
| ISBN (Electronic) | 978-1-5386-9395-7 |
| DOIs | |
| Publication status | Published - 17 Apr 2019 |
| Event | IEEE Custom Integrated Circuits Conference 2019 - Austin, United States Duration: 14 Apr 2019 → 17 Apr 2019 |
Publication series
| Name | Proceedings of the Custom Integrated Circuits Conference |
|---|---|
| Volume | 2019-April |
| ISSN (Print) | 0886-5930 |
Conference
| Conference | IEEE Custom Integrated Circuits Conference 2019 |
|---|---|
| Abbreviated title | CICC 2019 |
| Country | United States |
| City | Austin |
| Period | 14/04/19 → 17/04/19 |
Fingerprint
Keywords
- SAR ADC
- input buffer
- Class-A driver
- nyquist sampling
- SFDR
- INL
- DNL
Cite this
}
A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply. / Bindra, Harijot Singh; Annema, Anne J.; Wienk, Gerhardus J.M.; Nauta, Bram ; Louwsma, Simon.
2019 IEEE Custom Integrated Circuits Conference (CICC) . Austin, TX, USA : IEEE, 2019. 8780150 (Proceedings of the Custom Integrated Circuits Conference; Vol. 2019-April).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
TY - GEN
T1 - A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply
AU - Bindra, Harijot Singh
AU - Annema, Anne J.
AU - Wienk, Gerhardus J.M.
AU - Nauta, Bram
AU - Louwsma, Simon
PY - 2019/4/17
Y1 - 2019/4/17
N2 - We present a 10b differential SAR ADC integrated with unity gain (Class-A) voltage buffers, operating from a single supply voltage 1.2V and handling near rail-to-rail inputs. The two differential inputs are first compared and depending on the comparison result, the inputs are either swapped or not, after which these signals are buffered, sampled and converted. This way each of the two buffers needs to handle only half of the full-scale range which enables operation of the Class-A buffers at the ADC supply voltage while providing an overall near rail-to-rail (full-scale) input range for conversion. The buffered ADC can handle 2V P-P differential input and consumes 149μW at 4MS/s to achieve a state-of-the-art Walden FoM of 87fJ/conversion-step including buffers. The buffered ADC was designed in a 65nm CMOS process and occupies an active area of 0.04mm 2.
AB - We present a 10b differential SAR ADC integrated with unity gain (Class-A) voltage buffers, operating from a single supply voltage 1.2V and handling near rail-to-rail inputs. The two differential inputs are first compared and depending on the comparison result, the inputs are either swapped or not, after which these signals are buffered, sampled and converted. This way each of the two buffers needs to handle only half of the full-scale range which enables operation of the Class-A buffers at the ADC supply voltage while providing an overall near rail-to-rail (full-scale) input range for conversion. The buffered ADC can handle 2V P-P differential input and consumes 149μW at 4MS/s to achieve a state-of-the-art Walden FoM of 87fJ/conversion-step including buffers. The buffered ADC was designed in a 65nm CMOS process and occupies an active area of 0.04mm 2.
KW - SAR ADC
KW - input buffer
KW - Class-A driver
KW - nyquist sampling
KW - SFDR
KW - INL
KW - DNL
UR - http://www.scopus.com/inward/record.url?scp=85070564112&partnerID=8YFLogxK
U2 - 10.1109/CICC.2019.8780150
DO - 10.1109/CICC.2019.8780150
M3 - Conference contribution
T3 - Proceedings of the Custom Integrated Circuits Conference
BT - 2019 IEEE Custom Integrated Circuits Conference (CICC)
PB - IEEE
CY - Austin, TX, USA
ER -