A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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    Abstract

    We present a 10b differential SAR ADC integrated with unity gain (Class-A) voltage buffers, operating from a single supply voltage 1.2V and handling near rail-to-rail inputs. The two differential inputs are first compared and depending on the comparison result, the inputs are either swapped or not, after which these signals are buffered, sampled and converted. This way each of the two buffers needs to handle only half of the full-scale range which enables operation of the Class-A buffers at the ADC supply voltage while providing an overall near rail-to-rail (full-scale) input range for conversion. The buffered ADC can handle 2V P-P differential input and consumes 149μW at 4MS/s to achieve a state-of-the-art Walden FoM of 87fJ/conversion-step including buffers. The buffered ADC was designed in a 65nm CMOS process and occupies an active area of 0.04mm 2.

    Original languageEnglish
    Title of host publication2019 IEEE Custom Integrated Circuits Conference (CICC)
    Place of PublicationAustin, TX, USA
    PublisherIEEE
    ISBN (Electronic)978-1-5386-9395-7
    DOIs
    Publication statusPublished - 17 Apr 2019
    EventIEEE Custom Integrated Circuits Conference 2019 - Austin, United States
    Duration: 14 Apr 201917 Apr 2019

    Publication series

    NameProceedings of the Custom Integrated Circuits Conference
    Volume2019-April
    ISSN (Print)0886-5930

    Conference

    ConferenceIEEE Custom Integrated Circuits Conference 2019
    Abbreviated titleCICC 2019
    CountryUnited States
    CityAustin
    Period14/04/1917/04/19

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    Keywords

    • SAR ADC
    • input buffer
    • Class-A driver
    • nyquist sampling
    • SFDR
    • INL
    • DNL

    Cite this

    Bindra, H. S., Annema, A. J., Wienk, G. J. M., Nauta, B., & Louwsma, S. (2019). A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply. In 2019 IEEE Custom Integrated Circuits Conference (CICC) [8780150] (Proceedings of the Custom Integrated Circuits Conference; Vol. 2019-April). Austin, TX, USA: IEEE. https://doi.org/10.1109/CICC.2019.8780150
    Bindra, Harijot Singh ; Annema, Anne J. ; Wienk, Gerhardus J.M. ; Nauta, Bram ; Louwsma, Simon. / A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply. 2019 IEEE Custom Integrated Circuits Conference (CICC) . Austin, TX, USA : IEEE, 2019. (Proceedings of the Custom Integrated Circuits Conference).
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    title = "A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply",
    abstract = "We present a 10b differential SAR ADC integrated with unity gain (Class-A) voltage buffers, operating from a single supply voltage 1.2V and handling near rail-to-rail inputs. The two differential inputs are first compared and depending on the comparison result, the inputs are either swapped or not, after which these signals are buffered, sampled and converted. This way each of the two buffers needs to handle only half of the full-scale range which enables operation of the Class-A buffers at the ADC supply voltage while providing an overall near rail-to-rail (full-scale) input range for conversion. The buffered ADC can handle 2V P-P differential input and consumes 149μW at 4MS/s to achieve a state-of-the-art Walden FoM of 87fJ/conversion-step including buffers. The buffered ADC was designed in a 65nm CMOS process and occupies an active area of 0.04mm 2.",
    keywords = "SAR ADC, input buffer, Class-A driver, nyquist sampling, SFDR, INL, DNL",
    author = "Bindra, {Harijot Singh} and Annema, {Anne J.} and Wienk, {Gerhardus J.M.} and Bram Nauta and Simon Louwsma",
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    doi = "10.1109/CICC.2019.8780150",
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    Bindra, HS, Annema, AJ, Wienk, GJM, Nauta, B & Louwsma, S 2019, A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply. in 2019 IEEE Custom Integrated Circuits Conference (CICC) ., 8780150, Proceedings of the Custom Integrated Circuits Conference, vol. 2019-April, IEEE, Austin, TX, USA, IEEE Custom Integrated Circuits Conference 2019 , Austin, United States, 14/04/19. https://doi.org/10.1109/CICC.2019.8780150

    A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply. / Bindra, Harijot Singh; Annema, Anne J.; Wienk, Gerhardus J.M.; Nauta, Bram ; Louwsma, Simon.

    2019 IEEE Custom Integrated Circuits Conference (CICC) . Austin, TX, USA : IEEE, 2019. 8780150 (Proceedings of the Custom Integrated Circuits Conference; Vol. 2019-April).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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    N2 - We present a 10b differential SAR ADC integrated with unity gain (Class-A) voltage buffers, operating from a single supply voltage 1.2V and handling near rail-to-rail inputs. The two differential inputs are first compared and depending on the comparison result, the inputs are either swapped or not, after which these signals are buffered, sampled and converted. This way each of the two buffers needs to handle only half of the full-scale range which enables operation of the Class-A buffers at the ADC supply voltage while providing an overall near rail-to-rail (full-scale) input range for conversion. The buffered ADC can handle 2V P-P differential input and consumes 149μW at 4MS/s to achieve a state-of-the-art Walden FoM of 87fJ/conversion-step including buffers. The buffered ADC was designed in a 65nm CMOS process and occupies an active area of 0.04mm 2.

    AB - We present a 10b differential SAR ADC integrated with unity gain (Class-A) voltage buffers, operating from a single supply voltage 1.2V and handling near rail-to-rail inputs. The two differential inputs are first compared and depending on the comparison result, the inputs are either swapped or not, after which these signals are buffered, sampled and converted. This way each of the two buffers needs to handle only half of the full-scale range which enables operation of the Class-A buffers at the ADC supply voltage while providing an overall near rail-to-rail (full-scale) input range for conversion. The buffered ADC can handle 2V P-P differential input and consumes 149μW at 4MS/s to achieve a state-of-the-art Walden FoM of 87fJ/conversion-step including buffers. The buffered ADC was designed in a 65nm CMOS process and occupies an active area of 0.04mm 2.

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    PB - IEEE

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    Bindra HS, Annema AJ, Wienk GJM, Nauta B, Louwsma S. A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply. In 2019 IEEE Custom Integrated Circuits Conference (CICC) . Austin, TX, USA: IEEE. 2019. 8780150. (Proceedings of the Custom Integrated Circuits Conference). https://doi.org/10.1109/CICC.2019.8780150