A 65nm CMOS 1-to-10GHz tunable continuous-time low-pass filter for high-data-rate communications

F. Houfaf, Mathieu Egot, Andreas Kaiser, Andreia Cathelin, Bram Nauta

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

20 Citations (Scopus)
47 Downloads (Pure)

Abstract

In this work the Gm-C topology is adopted for its merits at high frequencies. In this technique, two critical parameters should be accounted for: the accuracy of the Q factors of the pole pairs (for correct transfer function) and parasitic capacitances (for maximal cut-off frequency). The former point is influenced by the phase shift of the integrators compounding the filter in the neighborhood of the filter's edge frequency. This phase error is due to two antagonistic effects which are the integrator's finite DC gain and its high-frequency poles/zeros.
Original languageEnglish
Title of host publicationIEEE International Solid-State Circuits Conference Digest of Technical Papers, ISSCC 2012
Place of PublicationPiscataway
PublisherIEEE
Pages362-364
Number of pages3
ISBN (Print)978-1-4673-0376-7
DOIs
Publication statusPublished - 19 Feb 2012
EventIEEE International Solid-State Circuits Conference, ISSCC 2012 - San Francisco, United States
Duration: 19 Feb 201223 Feb 2012

Conference

ConferenceIEEE International Solid-State Circuits Conference, ISSCC 2012
Abbreviated titleISSCC
CountryUnited States
CitySan Francisco
Period19/02/1223/02/12

Fingerprint

Low pass filters
Poles
Communication
Cutoff frequency
Phase shift
Transfer functions
Capacitance
Topology

Keywords

  • IR-80241
  • EWI-21783
  • METIS-286335

Cite this

Houfaf, F., Egot, M., Kaiser, A., Cathelin, A., & Nauta, B. (2012). A 65nm CMOS 1-to-10GHz tunable continuous-time low-pass filter for high-data-rate communications. In IEEE International Solid-State Circuits Conference Digest of Technical Papers, ISSCC 2012 (pp. 362-364). Piscataway: IEEE. https://doi.org/10.1109/ISSCC.2012.6177052
Houfaf, F. ; Egot, Mathieu ; Kaiser, Andreas ; Cathelin, Andreia ; Nauta, Bram. / A 65nm CMOS 1-to-10GHz tunable continuous-time low-pass filter for high-data-rate communications. IEEE International Solid-State Circuits Conference Digest of Technical Papers, ISSCC 2012. Piscataway : IEEE, 2012. pp. 362-364
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Houfaf, F, Egot, M, Kaiser, A, Cathelin, A & Nauta, B 2012, A 65nm CMOS 1-to-10GHz tunable continuous-time low-pass filter for high-data-rate communications. in IEEE International Solid-State Circuits Conference Digest of Technical Papers, ISSCC 2012. IEEE, Piscataway, pp. 362-364, IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, United States, 19/02/12. https://doi.org/10.1109/ISSCC.2012.6177052

A 65nm CMOS 1-to-10GHz tunable continuous-time low-pass filter for high-data-rate communications. / Houfaf, F.; Egot, Mathieu; Kaiser, Andreas; Cathelin, Andreia; Nauta, Bram.

IEEE International Solid-State Circuits Conference Digest of Technical Papers, ISSCC 2012. Piscataway : IEEE, 2012. p. 362-364.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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AB - In this work the Gm-C topology is adopted for its merits at high frequencies. In this technique, two critical parameters should be accounted for: the accuracy of the Q factors of the pole pairs (for correct transfer function) and parasitic capacitances (for maximal cut-off frequency). The former point is influenced by the phase shift of the integrators compounding the filter in the neighborhood of the filter's edge frequency. This phase error is due to two antagonistic effects which are the integrator's finite DC gain and its high-frequency poles/zeros.

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Houfaf F, Egot M, Kaiser A, Cathelin A, Nauta B. A 65nm CMOS 1-to-10GHz tunable continuous-time low-pass filter for high-data-rate communications. In IEEE International Solid-State Circuits Conference Digest of Technical Papers, ISSCC 2012. Piscataway: IEEE. 2012. p. 362-364 https://doi.org/10.1109/ISSCC.2012.6177052