A 70 MSample/s 110 mW 8 b CMOS folding interpolating A/D Converter

Bram Nauta, A.G.W. Venes

    Research output: Contribution to conferencePaper

    13 Citations (Scopus)
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    In bipolar technology the folding and interpolation technique has proven to be successful for high sample rates. This paper investigates the possibilities of this technique in CMOS. The major advantage of folding and interpolation in CMOS lies in the field of high sample rate in combination with low power consumption and small chip area. The folding converter requires little power to drive the input compared to other converters since the input behaves like a linear and constant capacitor. For similar reasons the power consumption of the reference ladder of the folding converter can be kept low. The circuit reported here runs at 70 MSample/s and dissipates only 110 mW. There are versions for 5 V and 3.3 V supplies and they are realized in a 0.8 μm CMOS process.
    Original languageUndefined
    Publication statusPublished - 1995
    EventIEEE International Solid-State Circuits Conference, ISSCC 1995 - San Francisco, United States
    Duration: 15 Feb 199517 Feb 1995


    ConferenceIEEE International Solid-State Circuits Conference, ISSCC 1995
    Abbreviated titleISSCC
    Country/TerritoryUnited States
    CitySan Francisco


    • IR-57311

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