A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter

Bram Nauta; Ardie G.W. Venes

doi:10.1109/4.482155

A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter

Bram Nauta, Ardie G.W. Venes

University of Twente

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100 Citations (Scopus)

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Abstract

A CMOS analog to digital converter based on the folding and interpolating technique is presented. This technique is successfully applied in bipolar A/D converters and now also becomes available in CMOS technology. The analog bandwidth of the A/D converter is increased by using a transresistance amplifier at the outputs of the folding amplifiers and, due to careful circuit design, the comparators need no offset compensation. The result is a small area (0.7 mm2 in 0.8 μm CMOS), high speed (70 MS/s), and low-power (110 mW at 5 V supply, including reference ladder) A/D converter. A 3.3 V supply version of the circuit runs at 45 MS/s and dissipates 45 mW.

Original language	Undefined
Pages (from-to)	1302-1308
Journal	IEEE journal of solid-state circuits
Volume	30
Issue number	12
DOIs	https://doi.org/10.1109/4.482155
Publication status	Published - 1995

Keywords

IR-57299

Access to Document

10.1109/4.482155

70-MS

Cite this

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title = "A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter",

abstract = "A CMOS analog to digital converter based on the folding and interpolating technique is presented. This technique is successfully applied in bipolar A/D converters and now also becomes available in CMOS technology. The analog bandwidth of the A/D converter is increased by using a transresistance amplifier at the outputs of the folding amplifiers and, due to careful circuit design, the comparators need no offset compensation. The result is a small area (0.7 mm2 in 0.8 μm CMOS), high speed (70 MS/s), and low-power (110 mW at 5 V supply, including reference ladder) A/D converter. A 3.3 V supply version of the circuit runs at 45 MS/s and dissipates 45 mW.",

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T1 - A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter

AU - Nauta, Bram

AU - Venes, Ardie G.W.

PY - 1995

Y1 - 1995

N2 - A CMOS analog to digital converter based on the folding and interpolating technique is presented. This technique is successfully applied in bipolar A/D converters and now also becomes available in CMOS technology. The analog bandwidth of the A/D converter is increased by using a transresistance amplifier at the outputs of the folding amplifiers and, due to careful circuit design, the comparators need no offset compensation. The result is a small area (0.7 mm2 in 0.8 μm CMOS), high speed (70 MS/s), and low-power (110 mW at 5 V supply, including reference ladder) A/D converter. A 3.3 V supply version of the circuit runs at 45 MS/s and dissipates 45 mW.

AB - A CMOS analog to digital converter based on the folding and interpolating technique is presented. This technique is successfully applied in bipolar A/D converters and now also becomes available in CMOS technology. The analog bandwidth of the A/D converter is increased by using a transresistance amplifier at the outputs of the folding amplifiers and, due to careful circuit design, the comparators need no offset compensation. The result is a small area (0.7 mm2 in 0.8 μm CMOS), high speed (70 MS/s), and low-power (110 mW at 5 V supply, including reference ladder) A/D converter. A 3.3 V supply version of the circuit runs at 45 MS/s and dissipates 45 mW.

KW - IR-57299

U2 - 10.1109/4.482155

DO - 10.1109/4.482155

M3 - Article

SN - 0018-9200

VL - 30

SP - 1302

EP - 1308

JO - IEEE journal of solid-state circuits

JF - IEEE journal of solid-state circuits

IS - 12

ER -