A buried-channel CCD is presented, suitable for integration in a high-energy ion-implanted CMOS process. The BCCD channel is high-energy ion-implanted and the gate structure is non-overlapping. The required submicron spacings between adjacent gates are created by a sequence of processing steps. No demands are imposed on the lithography used. SEM photographs show a well-defined gate structure with straight spacings exhibiting minor width variation. The parasitic potential well, associated with the presence of spacing between the gates, has little influence on charge transport performance. Delay lines have been operated with transfer inefficiency of 10-5 and less.