A CMOS analog continuous-time delay-line

Klaas Bult, Hans Wallinga

Research output: Contribution to conferencePaperAcademic

11 Downloads (Pure)

Abstract

A current-domain first-order all-pass filter-section has been developed, composed of a single capacitor and CMOS circuits with linear resistive input impedance, based on the square-law characteristic of an MOS transistor in saturation. Experimental verification has been performed by means of an integrated cascade of 26 identical all-pass sections acting as a continuous-time delay-line.
Original languageUndefined
Pages35-38
Publication statusPublished - 1987
Event13th European Solid-state Circuits Conference, ESSCIRC 1987 - Taunus-Tagungs-Zentrum, Friedrichsdorf, Germany
Duration: 23 Sep 198725 Sep 1987
Conference number: 13

Conference

Conference13th European Solid-state Circuits Conference, ESSCIRC 1987
Abbreviated titleESSCIRC
CountryGermany
CityFriedrichsdorf
Period23/09/8725/09/87

Keywords

  • IR-96392

Cite this

Bult, K., & Wallinga, H. (1987). A CMOS analog continuous-time delay-line. 35-38. Paper presented at 13th European Solid-state Circuits Conference, ESSCIRC 1987, Friedrichsdorf, Germany.
Bult, Klaas ; Wallinga, Hans. / A CMOS analog continuous-time delay-line. Paper presented at 13th European Solid-state Circuits Conference, ESSCIRC 1987, Friedrichsdorf, Germany.
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author = "Klaas Bult and Hans Wallinga",
year = "1987",
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Bult, K & Wallinga, H 1987, 'A CMOS analog continuous-time delay-line' Paper presented at 13th European Solid-state Circuits Conference, ESSCIRC 1987, Friedrichsdorf, Germany, 23/09/87 - 25/09/87, pp. 35-38.

A CMOS analog continuous-time delay-line. / Bult, Klaas; Wallinga, Hans.

1987. 35-38 Paper presented at 13th European Solid-state Circuits Conference, ESSCIRC 1987, Friedrichsdorf, Germany.

Research output: Contribution to conferencePaperAcademic

TY - CONF

T1 - A CMOS analog continuous-time delay-line

AU - Bult, Klaas

AU - Wallinga, Hans

PY - 1987

Y1 - 1987

N2 - A current-domain first-order all-pass filter-section has been developed, composed of a single capacitor and CMOS circuits with linear resistive input impedance, based on the square-law characteristic of an MOS transistor in saturation. Experimental verification has been performed by means of an integrated cascade of 26 identical all-pass sections acting as a continuous-time delay-line.

AB - A current-domain first-order all-pass filter-section has been developed, composed of a single capacitor and CMOS circuits with linear resistive input impedance, based on the square-law characteristic of an MOS transistor in saturation. Experimental verification has been performed by means of an integrated cascade of 26 identical all-pass sections acting as a continuous-time delay-line.

KW - IR-96392

M3 - Paper

SP - 35

EP - 38

ER -

Bult K, Wallinga H. A CMOS analog continuous-time delay-line. 1987. Paper presented at 13th European Solid-state Circuits Conference, ESSCIRC 1987, Friedrichsdorf, Germany.