A CMOS analog continuous-time delay-line

Klaas Bult; Hans Wallinga

A CMOS analog continuous-time delay-line

Klaas Bult, Hans Wallinga

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Abstract

A current-domain first-order all-pass filter-section has been developed, composed of a single capacitor and CMOS circuits with linear resistive input impedance, based on the square-law characteristic of an MOS transistor in saturation. Experimental verification has been performed by means of an integrated cascade of 26 identical all-pass sections acting as a continuous-time delay-line.

Original language	English
Pages	35-38
Publication status	Published - 1987
Event	13th European Solid-state Circuits Conference, ESSCIRC 1987 - Taunus-Tagungs-Zentrum, Friedrichsdorf, Germany Duration: 23 Sept 1987 → 25 Sept 1987 Conference number: 13

Conference

Conference	13th European Solid-state Circuits Conference, ESSCIRC 1987
Abbreviated title	ESSCIRC
Country/Territory	Germany
City	Friedrichsdorf
Period	23/09/87 → 25/09/87

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https://ieeexplore.ieee.org/document/5434957

Cite this

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title = "A CMOS analog continuous-time delay-line",

abstract = "A current-domain first-order all-pass filter-section has been developed, composed of a single capacitor and CMOS circuits with linear resistive input impedance, based on the square-law characteristic of an MOS transistor in saturation. Experimental verification has been performed by means of an integrated cascade of 26 identical all-pass sections acting as a continuous-time delay-line.",

author = "Klaas Bult and Hans Wallinga",

year = "1987",

language = "English",

pages = "35--38",

note = "13th European Solid-state Circuits Conference, ESSCIRC 1987, ESSCIRC ; Conference date: 23-09-1987 Through 25-09-1987",

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TY - CONF

T1 - A CMOS analog continuous-time delay-line

AU - Bult, Klaas

AU - Wallinga, Hans

N1 - Conference code: 13

PY - 1987

Y1 - 1987

N2 - A current-domain first-order all-pass filter-section has been developed, composed of a single capacitor and CMOS circuits with linear resistive input impedance, based on the square-law characteristic of an MOS transistor in saturation. Experimental verification has been performed by means of an integrated cascade of 26 identical all-pass sections acting as a continuous-time delay-line.

AB - A current-domain first-order all-pass filter-section has been developed, composed of a single capacitor and CMOS circuits with linear resistive input impedance, based on the square-law characteristic of an MOS transistor in saturation. Experimental verification has been performed by means of an integrated cascade of 26 identical all-pass sections acting as a continuous-time delay-line.

M3 - Paper

SP - 35

EP - 38

T2 - 13th European Solid-state Circuits Conference, ESSCIRC 1987

Y2 - 23 September 1987 through 25 September 1987

ER -

A CMOS analog continuous-time delay-line

Abstract

Conference

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Cite this