A CMOS analog continuous-time delay-line

Klaas Bult, Hans Wallinga

    Research output: Contribution to conferencePaper

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    Abstract

    A current-domain first-order all-pass filter-section has been developed, composed of a single capacitor and CMOS circuits with linear resistive input impedance, based on the square-law characteristic of an MOS transistor in saturation. Experimental verification has been performed by means of an integrated cascade of 26 identical all-pass sections acting as a continuous-time delay-line.
    Original languageEnglish
    Pages35-38
    Publication statusPublished - 1987
    Event13th European Solid-state Circuits Conference, ESSCIRC 1987 - Taunus-Tagungs-Zentrum, Friedrichsdorf, Germany
    Duration: 23 Sep 198725 Sep 1987
    Conference number: 13

    Conference

    Conference13th European Solid-state Circuits Conference, ESSCIRC 1987
    Abbreviated titleESSCIRC
    CountryGermany
    CityFriedrichsdorf
    Period23/09/8725/09/87

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    Bult, K., & Wallinga, H. (1987). A CMOS analog continuous-time delay-line. 35-38. Paper presented at 13th European Solid-state Circuits Conference, ESSCIRC 1987, Friedrichsdorf, Germany.