A CMOS analog continuous-time delay line with adaptive delay-time control

Klaas Bult, Hans Wallinga

Research output: Contribution to journalArticleAcademic

30 Citations (Scopus)
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Abstract

A CMOS analog continuous-time delay line composed of cascaded first-order current-domain all-pass sections is discussed. Each all-pass section consists of CMOS transistors and a single capacitor. The operation is based on the square-law characteristic of an MOS transistor in saturation. The delay time per section can either be controlled by an external voltage or locked to an external reference frequency by means of a control system which features a large capture range. Experimental verification has been performed on two setups: an integrated cascade of 26 identical all-pass sections and a frequency-locking system breadboard built around two identical on-chip all-pass sections
Original languageUndefined
Pages (from-to)759-766
JournalIEEE journal of solid-state circuits
Volume23
Issue number3
DOIs
Publication statusPublished - 1988

Keywords

  • IR-55781

Cite this

Bult, Klaas ; Wallinga, Hans. / A CMOS analog continuous-time delay line with adaptive delay-time control. In: IEEE journal of solid-state circuits. 1988 ; Vol. 23, No. 3. pp. 759-766.
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A CMOS analog continuous-time delay line with adaptive delay-time control. / Bult, Klaas; Wallinga, Hans.

In: IEEE journal of solid-state circuits, Vol. 23, No. 3, 1988, p. 759-766.

Research output: Contribution to journalArticleAcademic

TY - JOUR

T1 - A CMOS analog continuous-time delay line with adaptive delay-time control

AU - Bult, Klaas

AU - Wallinga, Hans

PY - 1988

Y1 - 1988

N2 - A CMOS analog continuous-time delay line composed of cascaded first-order current-domain all-pass sections is discussed. Each all-pass section consists of CMOS transistors and a single capacitor. The operation is based on the square-law characteristic of an MOS transistor in saturation. The delay time per section can either be controlled by an external voltage or locked to an external reference frequency by means of a control system which features a large capture range. Experimental verification has been performed on two setups: an integrated cascade of 26 identical all-pass sections and a frequency-locking system breadboard built around two identical on-chip all-pass sections

AB - A CMOS analog continuous-time delay line composed of cascaded first-order current-domain all-pass sections is discussed. Each all-pass section consists of CMOS transistors and a single capacitor. The operation is based on the square-law characteristic of an MOS transistor in saturation. The delay time per section can either be controlled by an external voltage or locked to an external reference frequency by means of a control system which features a large capture range. Experimental verification has been performed on two setups: an integrated cascade of 26 identical all-pass sections and a frequency-locking system breadboard built around two identical on-chip all-pass sections

KW - IR-55781

U2 - 10.1109/4.316

DO - 10.1109/4.316

M3 - Article

VL - 23

SP - 759

EP - 766

JO - IEEE journal of solid-state circuits

JF - IEEE journal of solid-state circuits

SN - 0018-9200

IS - 3

ER -