Abstract
A CMOS analog continuous-time delay line composed of cascaded first-order current-domain all-pass sections is discussed. Each all-pass section consists of CMOS transistors and a single capacitor. The operation is based on the square-law characteristic of an MOS transistor in saturation. The delay time per section can either be controlled by an external voltage or locked to an external reference frequency by means of a control system which features a large capture range. Experimental verification has been performed on two setups: an integrated cascade of 26 identical all-pass sections and a frequency-locking system breadboard built around two identical on-chip all-pass sections
| Original language | English |
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| Pages (from-to) | 759-766 |
| Journal | IEEE journal of solid-state circuits |
| Volume | 23 |
| Issue number | 3 |
| DOIs | |
| Publication status | Published - 1988 |