A CMOS four-quadrant analog current multiplier

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    18 Citations (Scopus)
    141 Downloads (Pure)

    Abstract

    A CMOS four-quadrant analog current multiplier is described. The circuit is based on the square-law characteristic of an MOS transistor and is insensitive to temperature and process variations. The circuit is insensitive to the body effect so it is not necessary to place transistors in individual wells. The multiplier has a large -3-dB bandwidth (50 MHz with 10-¿m transistors) and an approximately constant input impedance. The circuit was realized on a CMOS semicustom array. Measurements have shown that the nonlinearity is less than 1% at the maximum input current range and less than 0.2% when the input range is restricted to 50% of the maximum
    Original languageUndefined
    Title of host publicationISCAS-Conference
    Place of PublicationSingapore
    PublisherIEEE
    Pages2244-2247
    Number of pages4
    DOIs
    Publication statusPublished - 11 Jun 1991
    EventIEEE International Symposium on Circuits and Systems, ISCAS 1991 - Singapore, Singapore
    Duration: 11 Jun 199114 Jun 1991

    Publication series

    Name
    PublisherIEEE
    Volume4

    Conference

    ConferenceIEEE International Symposium on Circuits and Systems, ISCAS 1991
    Abbreviated titleISCAS
    CountrySingapore
    CitySingapore
    Period11/06/9114/06/91

    Keywords

    • METIS-113941
    • IR-17056

    Cite this

    Wiegerink, Remco J. / A CMOS four-quadrant analog current multiplier. ISCAS-Conference. Singapore : IEEE, 1991. pp. 2244-2247
    @inproceedings{e9fefce37d064b09b7abe97a59268766,
    title = "A CMOS four-quadrant analog current multiplier",
    abstract = "A CMOS four-quadrant analog current multiplier is described. The circuit is based on the square-law characteristic of an MOS transistor and is insensitive to temperature and process variations. The circuit is insensitive to the body effect so it is not necessary to place transistors in individual wells. The multiplier has a large -3-dB bandwidth (50 MHz with 10-¿m transistors) and an approximately constant input impedance. The circuit was realized on a CMOS semicustom array. Measurements have shown that the nonlinearity is less than 1{\%} at the maximum input current range and less than 0.2{\%} when the input range is restricted to 50{\%} of the maximum",
    keywords = "METIS-113941, IR-17056",
    author = "Wiegerink, {Remco J.}",
    year = "1991",
    month = "6",
    day = "11",
    doi = "10.1109/ISCAS.1991.176826",
    language = "Undefined",
    publisher = "IEEE",
    pages = "2244--2247",
    booktitle = "ISCAS-Conference",
    address = "United States",

    }

    Wiegerink, RJ 1991, A CMOS four-quadrant analog current multiplier. in ISCAS-Conference. IEEE, Singapore, pp. 2244-2247, IEEE International Symposium on Circuits and Systems, ISCAS 1991, Singapore, Singapore, 11/06/91. https://doi.org/10.1109/ISCAS.1991.176826

    A CMOS four-quadrant analog current multiplier. / Wiegerink, Remco J.

    ISCAS-Conference. Singapore : IEEE, 1991. p. 2244-2247.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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    N2 - A CMOS four-quadrant analog current multiplier is described. The circuit is based on the square-law characteristic of an MOS transistor and is insensitive to temperature and process variations. The circuit is insensitive to the body effect so it is not necessary to place transistors in individual wells. The multiplier has a large -3-dB bandwidth (50 MHz with 10-¿m transistors) and an approximately constant input impedance. The circuit was realized on a CMOS semicustom array. Measurements have shown that the nonlinearity is less than 1% at the maximum input current range and less than 0.2% when the input range is restricted to 50% of the maximum

    AB - A CMOS four-quadrant analog current multiplier is described. The circuit is based on the square-law characteristic of an MOS transistor and is insensitive to temperature and process variations. The circuit is insensitive to the body effect so it is not necessary to place transistors in individual wells. The multiplier has a large -3-dB bandwidth (50 MHz with 10-¿m transistors) and an approximately constant input impedance. The circuit was realized on a CMOS semicustom array. Measurements have shown that the nonlinearity is less than 1% at the maximum input current range and less than 0.2% when the input range is restricted to 50% of the maximum

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