A CMOS four-quadrant analog multiplier

Klaas Bult; Hans Wallinga

doi:10.1109/JSSC.1986.1052546

A CMOS four-quadrant analog multiplier

Klaas Bult, Hans Wallinga

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Abstract

A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law characteristics of the MOS transistor. Two versions have been realized. The first has a linearity better than 0.14 percent for an output current swing of 36 percent of the supply current and a bandwidth from dc to 1 MHz. The second version has floating inputs, a linearity of 0.4 percent at an output current swing of 40 percent of the supply current and a bandwidth from dc to above 4.5 MHz.

Original language	English
Pages (from-to)	430-435
Journal	IEEE journal of solid-state circuits
Volume	21
Issue number	3
DOIs	https://doi.org/10.1109/JSSC.1986.1052546
Publication status	Published - 1979

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title = "A CMOS four-quadrant analog multiplier",

abstract = "A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law characteristics of the MOS transistor. Two versions have been realized. The first has a linearity better than 0.14 percent for an output current swing of 36 percent of the supply current and a bandwidth from dc to 1 MHz. The second version has floating inputs, a linearity of 0.4 percent at an output current swing of 40 percent of the supply current and a bandwidth from dc to above 4.5 MHz.",

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AU - Wallinga, Hans

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AB - A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law characteristics of the MOS transistor. Two versions have been realized. The first has a linearity better than 0.14 percent for an output current swing of 36 percent of the supply current and a bandwidth from dc to 1 MHz. The second version has floating inputs, a linearity of 0.4 percent at an output current swing of 40 percent of the supply current and a bandwidth from dc to above 4.5 MHz.

U2 - 10.1109/JSSC.1986.1052546

DO - 10.1109/JSSC.1986.1052546

M3 - Article

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VL - 21

SP - 430

EP - 435

JO - IEEE journal of solid-state circuits

JF - IEEE journal of solid-state circuits

IS - 3

ER -

A CMOS four-quadrant analog multiplier

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