A CMOS four-quadrant analog multiplier

Klaas Bult, Hans Wallinga

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    Abstract

    A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law characteristics of the MOS transistor. Two versions have been realized. The first has a linearity better than 0.14 percent for an output current swing of 36 percent of the supply current and a bandwidth from dc to 1 MHz. The second version has floating inputs, a linearity of 0.4 percent at an output current swing of 40 percent of the supply current and a bandwidth from dc to above 4.5 MHz.
    Original languageUndefined
    Pages (from-to)430-435
    JournalIEEE journal of solid-state circuits
    Volume21
    Issue number3
    DOIs
    Publication statusPublished - 1979

    Keywords

    • IR-56126

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