A CMOS four-quadrant analog multiplier

Klaas Bult, Hans Wallinga

    Research output: Contribution to journalArticleAcademic

    98 Citations (Scopus)
    201 Downloads (Pure)

    Abstract

    A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law characteristics of the MOS transistor. Two versions have been realized. The first has a linearity better than 0.14 percent for an output current swing of 36 percent of the supply current and a bandwidth from dc to 1 MHz. The second version has floating inputs, a linearity of 0.4 percent at an output current swing of 40 percent of the supply current and a bandwidth from dc to above 4.5 MHz.
    Original languageUndefined
    Pages (from-to)430-435
    JournalIEEE journal of solid-state circuits
    Volume21
    Issue number3
    DOIs
    Publication statusPublished - 1979

    Keywords

    • IR-56126

    Cite this

    Bult, Klaas ; Wallinga, Hans. / A CMOS four-quadrant analog multiplier. In: IEEE journal of solid-state circuits. 1979 ; Vol. 21, No. 3. pp. 430-435.
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    A CMOS four-quadrant analog multiplier. / Bult, Klaas; Wallinga, Hans.

    In: IEEE journal of solid-state circuits, Vol. 21, No. 3, 1979, p. 430-435.

    Research output: Contribution to journalArticleAcademic

    TY - JOUR

    T1 - A CMOS four-quadrant analog multiplier

    AU - Bult, Klaas

    AU - Wallinga, Hans

    PY - 1979

    Y1 - 1979

    N2 - A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law characteristics of the MOS transistor. Two versions have been realized. The first has a linearity better than 0.14 percent for an output current swing of 36 percent of the supply current and a bandwidth from dc to 1 MHz. The second version has floating inputs, a linearity of 0.4 percent at an output current swing of 40 percent of the supply current and a bandwidth from dc to above 4.5 MHz.

    AB - A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law characteristics of the MOS transistor. Two versions have been realized. The first has a linearity better than 0.14 percent for an output current swing of 36 percent of the supply current and a bandwidth from dc to 1 MHz. The second version has floating inputs, a linearity of 0.4 percent at an output current swing of 40 percent of the supply current and a bandwidth from dc to above 4.5 MHz.

    KW - IR-56126

    U2 - 10.1109/JSSC.1986.1052546

    DO - 10.1109/JSSC.1986.1052546

    M3 - Article

    VL - 21

    SP - 430

    EP - 435

    JO - IEEE journal of solid-state circuits

    JF - IEEE journal of solid-state circuits

    SN - 0018-9200

    IS - 3

    ER -