A CMOS spectrum analyzer frontend for cognitive radio achieving +25dBm IIP3 and −169 dBm/Hz DANL

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    56 Downloads (Pure)

    Abstract

    A dual RF-receiver preceded by discrete-step attenuators is implemented in 65nm CMOS and operates from 0.3– 1.0 GHz. The noise of the receivers is reduced by cross-correlating the two receiver outputs in the digital baseband, allowing attenuation of the RF input signal to increase linearity. With this technique a displayed average noise level below -169 dBm/Hz is obtained with +25 dBm IIP3, giving a spurious-free dynamic range of 89 dB in 1 MHz resolution bandwidth.
    Original languageEnglish
    Title of host publicationIEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012
    Subtitle of host publicationMontréalm, Canada, 17-19 June 2012
    Place of PublicationPiscataway, NJ
    PublisherIEEE
    Pages35-38
    Number of pages4
    ISBN (Electronic)978-1-4673-0413-9, 978-1-4673-0416-0
    ISBN (Print)978-1-4673-0415-3
    DOIs
    Publication statusPublished - 17 Jun 2012
    Event2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012 - Palais des Congrès in Montreal, Montreal, Canada
    Duration: 17 Jun 201219 Jun 2012

    Conference

    Conference2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012
    Abbreviated titleRFIC
    CountryCanada
    CityMontreal
    Period17/06/1219/06/12

    Keywords

    • IR-81253
    • METIS-296075
    • IIP3
    • Crosscorrelation
    • Cognitive Radio
    • EWI-22177
    • noise figure
    • Spectrum Sensing
    • Linearity
    • spurious-free dynamic range
    • spectrum analyzer
    • energy detection

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