A communication model based on n-dimensional Torus Architecture using dead-lock-free wormhole routing

P.K.F. Holzenspies, Erik Schepers, Wouter Bach, Mischa Jonker, Bart Sikkes, Gerardus Johannes Maria Smit, Paul J.M. Havinga

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    4 Citations (Scopus)

    Abstract

    Routing on a two-dimensional torus architecture by means of the wormhole routing algorithm is introduced and extended to an n-dimensional torus model. To prevent blocking deadlocks caused by this algorithm, a multiple virtual channel solution is introduced. An implementation of virtual channels is introduced that allows channels with higher labels to pre-empt 'lower' channels. This algorithm is tested with a simplified model of a HiperLAN/2 receiver. The model proves to be capable of running this application on the Chameleon architecture according to http://chameleon.ctit.utwente.nl/.
    Original languageUndefined
    Title of host publicationProceedings Euromicro symposium on digital system design
    Place of PublicationBelek, Turkey
    PublisherIEEE Computer Society
    Pages166-172
    ISBN (Print)0-7695-2003-0
    DOIs
    Publication statusPublished - 2003
    Event6th EUROMICRO Symposium on Digital System Design, DSD 2003 - Belek, Turkey
    Duration: 1 Sep 20036 Sep 2003
    Conference number: 6

    Publication series

    Name
    PublisherIEEE Computer Society

    Conference

    Conference6th EUROMICRO Symposium on Digital System Design, DSD 2003
    Abbreviated titleDSD
    CountryTurkey
    CityBelek
    Period1/09/036/09/03

    Keywords

    • virtual channel
    • communication model
    • wormhole routing algorithm
    • deadlock-free wormhole routing
    • System-on-a-chip
    • System recovery
    • Testing
    • Tiles
    • blocking deadlocks
    • METIS-214849
    • IR-46387
    • Chameleon architecture
    • Computer Architecture
    • Computer Science
    • Routing
    • Hardware
    • Energy consumption
    • n-dimensional torus architecture
    • Reconfigurable architectures

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