A communication model based on n-dimensional Torus Architecture using dead-lock-free wormhole routing

P.K.F. Holzenspies; Erik Schepers; Wouter Bach; Mischa Jonker; Bart Sikkes; Gerardus Johannes Maria Smit; Paul J.M. Havinga

doi:10.1109/DSD.2003.1231920

A communication model based on n-dimensional Torus Architecture using dead-lock-free wormhole routing

P.K.F. Holzenspies
, Erik Schepers
, Wouter Bach
, Mischa Jonker
, Bart Sikkes
, Gerardus Johannes Maria Smit
, Paul J.M. Havinga

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

4 Citations (Scopus)

8 Downloads (Pure)

Abstract

Routing on a two-dimensional torus architecture by means of the wormhole routing algorithm is introduced and extended to an n-dimensional torus model. To prevent blocking deadlocks caused by this algorithm, a multiple virtual channel solution is introduced. An implementation of virtual channels is introduced that allows channels with higher labels to pre-empt 'lower' channels. This algorithm is tested with a simplified model of a HiperLAN/2 receiver. The model proves to be capable of running this application on the Chameleon architecture according to http://chameleon.ctit.utwente.nl/.

Original language	Undefined
Title of host publication	Proceedings Euromicro symposium on digital system design
Place of Publication	Belek, Turkey
Publisher	IEEE
Pages	166-172
ISBN (Print)	0-7695-2003-0
DOIs	https://doi.org/10.1109/DSD.2003.1231920
Publication status	Published - 2003
Event	6th EUROMICRO Symposium on Digital System Design, DSD 2003 - Belek, Turkey Duration: 1 Sept 2003 → 6 Sept 2003 Conference number: 6

Publication series

Name
Publisher	IEEE Computer Society

Conference

Conference	6th EUROMICRO Symposium on Digital System Design, DSD 2003
Abbreviated title	DSD
Country/Territory	Turkey
City	Belek
Period	1/09/03 → 6/09/03

Keywords

virtual channel
communication model
wormhole routing algorithm
deadlock-free wormhole routing
System-on-a-chip
System recovery
Testing
Tiles
blocking deadlocks
METIS-214849
IR-46387
Chameleon architecture
Computer Architecture
Computer Science
Routing
Hardware
Energy consumption
n-dimensional torus architecture
Reconfigurable architectures

Access to Document

10.1109/DSD.2003.1231920

Cite this

@inproceedings{a3979d277bca4bc1b91579f547501c67,

title = "A communication model based on n-dimensional Torus Architecture using dead-lock-free wormhole routing",

abstract = "Routing on a two-dimensional torus architecture by means of the wormhole routing algorithm is introduced and extended to an n-dimensional torus model. To prevent blocking deadlocks caused by this algorithm, a multiple virtual channel solution is introduced. An implementation of virtual channels is introduced that allows channels with higher labels to pre-empt 'lower' channels. This algorithm is tested with a simplified model of a HiperLAN/2 receiver. The model proves to be capable of running this application on the Chameleon architecture according to http://chameleon.ctit.utwente.nl/.",

keywords = "virtual channel, communication model, wormhole routing algorithm, deadlock-free wormhole routing, System-on-a-chip, System recovery, Testing, Tiles, blocking deadlocks, METIS-214849, IR-46387, Chameleon architecture, Computer Architecture, Computer Science, Routing, Hardware, Energy consumption, n-dimensional torus architecture, Reconfigurable architectures",

author = "P.K.F. Holzenspies and Erik Schepers and Wouter Bach and Mischa Jonker and Bart Sikkes and Smit, \{Gerardus Johannes Maria\} and Havinga, \{Paul J.M.\}",

year = "2003",

doi = "10.1109/DSD.2003.1231920",

language = "Undefined",

isbn = "0-7695-2003-0",

publisher = "IEEE",

pages = "166--172",

booktitle = "Proceedings Euromicro symposium on digital system design",

address = "United States",

note = "6th EUROMICRO Symposium on Digital System Design, DSD 2003 ; Conference date: 01-09-2003 Through 06-09-2003",

}

Holzenspies, PKF, Schepers, E, Bach, W, Jonker, M, Sikkes, B, Smit, GJM & Havinga, PJM 2003, A communication model based on n-dimensional Torus Architecture using dead-lock-free wormhole routing. in Proceedings Euromicro symposium on digital system design. IEEE, Belek, Turkey, pp. 166-172, 6th EUROMICRO Symposium on Digital System Design, DSD 2003, Belek, Turkey, 1/09/03. https://doi.org/10.1109/DSD.2003.1231920

A communication model based on n-dimensional Torus Architecture using dead-lock-free wormhole routing. / Holzenspies, P.K.F.; Schepers, Erik; Bach, Wouter et al.
Proceedings Euromicro symposium on digital system design. Belek, Turkey: IEEE, 2003. p. 166-172.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A communication model based on n-dimensional Torus Architecture using dead-lock-free wormhole routing

AU - Holzenspies, P.K.F.

AU - Schepers, Erik

AU - Bach, Wouter

AU - Jonker, Mischa

AU - Sikkes, Bart

AU - Smit, Gerardus Johannes Maria

AU - Havinga, Paul J.M.

N1 - Conference code: 6

PY - 2003

Y1 - 2003

N2 - Routing on a two-dimensional torus architecture by means of the wormhole routing algorithm is introduced and extended to an n-dimensional torus model. To prevent blocking deadlocks caused by this algorithm, a multiple virtual channel solution is introduced. An implementation of virtual channels is introduced that allows channels with higher labels to pre-empt 'lower' channels. This algorithm is tested with a simplified model of a HiperLAN/2 receiver. The model proves to be capable of running this application on the Chameleon architecture according to http://chameleon.ctit.utwente.nl/.

AB - Routing on a two-dimensional torus architecture by means of the wormhole routing algorithm is introduced and extended to an n-dimensional torus model. To prevent blocking deadlocks caused by this algorithm, a multiple virtual channel solution is introduced. An implementation of virtual channels is introduced that allows channels with higher labels to pre-empt 'lower' channels. This algorithm is tested with a simplified model of a HiperLAN/2 receiver. The model proves to be capable of running this application on the Chameleon architecture according to http://chameleon.ctit.utwente.nl/.

KW - virtual channel

KW - communication model

KW - wormhole routing algorithm

KW - deadlock-free wormhole routing

KW - System-on-a-chip

KW - System recovery

KW - Testing

KW - Tiles

KW - blocking deadlocks

KW - METIS-214849

KW - IR-46387

KW - Chameleon architecture

KW - Computer Architecture

KW - Computer Science

KW - Routing

KW - Hardware

KW - Energy consumption

KW - n-dimensional torus architecture

KW - Reconfigurable architectures

U2 - 10.1109/DSD.2003.1231920

DO - 10.1109/DSD.2003.1231920

M3 - Conference contribution

SN - 0-7695-2003-0

SP - 166

EP - 172

BT - Proceedings Euromicro symposium on digital system design

PB - IEEE

CY - Belek, Turkey

T2 - 6th EUROMICRO Symposium on Digital System Design, DSD 2003

Y2 - 1 September 2003 through 6 September 2003

ER -