A complete Digital Design and Test Flow in an Academic Environment

M.H.H. Weusthof; R.M.W. Tijink; H.G. Kerkhoff

A complete Digital Design and Test Flow in an Academic Environment

M.H.H. Weusthof
, R.M.W. Tijink
, H.G. Kerkhoff

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

This paper shows an automated flow to generate test vectors for digital IC-designs in an academic environment. The tool “Tetramax” from Synopsys has been used for Automatic Test Pattern Generation. The ATS200 hardware verification tester together with IMS software provides a structured environment for prototype analysis and for real-time comparison of the design performance against the simulated data output. Its diagnostic capabilities have been verified by hardware-based emulating stuck-at faults at various test points in a demonstrator chip and we subsequently traced
back the introduced fault successfully. The used flow simplifies the generation of test vectors and subsequent debugging, especially for large digital integrated circuits.

Original language	English
Title of host publication	Proceedings ProRISC 2002
Pages	551-555
Number of pages	5
Publication status	Published - 29 Nov 2002
Event	13th Workshop on Circuits, Systems and Signal Processing, ProRISC 2002 - Veldhoven, Netherlands Duration: 28 Nov 2002 → 29 Nov 2002 Conference number: 13

Workshop

Workshop	13th Workshop on Circuits, Systems and Signal Processing, ProRISC 2002
Country/Territory	Netherlands
City	Veldhoven
Period	28/11/02 → 29/11/02

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title = "A complete Digital Design and Test Flow in an Academic Environment",

abstract = "This paper shows an automated flow to generate test vectors for digital IC-designs in an academic environment. The tool “Tetramax” from Synopsys has been used for Automatic Test Pattern Generation. The ATS200 hardware verification tester together with IMS software provides a structured environment for prototype analysis and for real-time comparison of the design performance against the simulated data output. Its diagnostic capabilities have been verified by hardware-based emulating stuck-at faults at various test points in a demonstrator chip and we subsequently traced back the introduced fault successfully. The used flow simplifies the generation of test vectors and subsequent debugging, especially for large digital integrated circuits.",

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AB - This paper shows an automated flow to generate test vectors for digital IC-designs in an academic environment. The tool “Tetramax” from Synopsys has been used for Automatic Test Pattern Generation. The ATS200 hardware verification tester together with IMS software provides a structured environment for prototype analysis and for real-time comparison of the design performance against the simulated data output. Its diagnostic capabilities have been verified by hardware-based emulating stuck-at faults at various test points in a demonstrator chip and we subsequently traced back the introduced fault successfully. The used flow simplifies the generation of test vectors and subsequent debugging, especially for large digital integrated circuits.

M3 - Conference contribution

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BT - Proceedings ProRISC 2002

T2 - 13th Workshop on Circuits, Systems and Signal Processing, ProRISC 2002

Y2 - 28 November 2002 through 29 November 2002

ER -

A complete Digital Design and Test Flow in an Academic Environment

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