A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability

Saranyu Chattopadhyay, Pranesh Santikellur, Rajat Subhra Chakraborty, Jimson Mathew, Marco Ottavi

Research output: Contribution to journalArticleAcademicpeer-review

2 Citations (Scopus)


Physically Unclonable Function (PUF) circuits are promising low-overhead hardware security primitives, but are often gravely susceptible to machine learning-based modeling attacks. Recently, chaotic PUF circuits have been proposed that show greater robustness to modeling attacks. However, they often suffer from unacceptable overhead, and their analog components are susceptible to low reliability. In this article, we propose the concept of a conditionally chaotic PUF that enhances the reliability of the analog components of a chaotic PUF circuit to a level at par with their digital counterparts. A conditionally chaotic PUF has two modes of operation: bistable and chaotic, and switching between these two modes is conveniently achieved by setting a mode-control bit (at a secret position) in an applied input challenge. We exemplify our PUF design framework for two different PUF variants - the CMOS Arbiter PUF and a previously proposed hybrid CMOS-memristor PUF, combined with a hardware realization of the Lorenz system as the chaotic component. Through detailed circuit simulation and modeling attack experiments, we demonstrate that the proposed PUF circuits are highly robust to modeling and cryptanalytic attacks, without degrading the reliability of the original PUF that was combined with the chaotic circuit, and incurs acceptable hardware footprint.

Original languageEnglish
Article number3460004
JournalACM transactions on design automation of electronic systems
Issue number6
Early online date12 Aug 2021
Publication statusPublished - Nov 2021
Externally publishedYes


  • Chaotic PUF
  • hardware security
  • Lorenz chaotic system
  • machine learning-based modeling attack
  • memristor
  • physically unclonable function (PUF)


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