TY - JOUR
T1 - A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability
AU - Chattopadhyay, Saranyu
AU - Santikellur, Pranesh
AU - Chakraborty, Rajat Subhra
AU - Mathew, Jimson
AU - Ottavi, Marco
N1 - Publisher Copyright:
© 2021 Association for Computing Machinery.
PY - 2021/11
Y1 - 2021/11
N2 - Physically Unclonable Function (PUF) circuits are promising low-overhead hardware security primitives, but are often gravely susceptible to machine learning-based modeling attacks. Recently, chaotic PUF circuits have been proposed that show greater robustness to modeling attacks. However, they often suffer from unacceptable overhead, and their analog components are susceptible to low reliability. In this article, we propose the concept of a conditionally chaotic PUF that enhances the reliability of the analog components of a chaotic PUF circuit to a level at par with their digital counterparts. A conditionally chaotic PUF has two modes of operation: bistable and chaotic, and switching between these two modes is conveniently achieved by setting a mode-control bit (at a secret position) in an applied input challenge. We exemplify our PUF design framework for two different PUF variants - the CMOS Arbiter PUF and a previously proposed hybrid CMOS-memristor PUF, combined with a hardware realization of the Lorenz system as the chaotic component. Through detailed circuit simulation and modeling attack experiments, we demonstrate that the proposed PUF circuits are highly robust to modeling and cryptanalytic attacks, without degrading the reliability of the original PUF that was combined with the chaotic circuit, and incurs acceptable hardware footprint.
AB - Physically Unclonable Function (PUF) circuits are promising low-overhead hardware security primitives, but are often gravely susceptible to machine learning-based modeling attacks. Recently, chaotic PUF circuits have been proposed that show greater robustness to modeling attacks. However, they often suffer from unacceptable overhead, and their analog components are susceptible to low reliability. In this article, we propose the concept of a conditionally chaotic PUF that enhances the reliability of the analog components of a chaotic PUF circuit to a level at par with their digital counterparts. A conditionally chaotic PUF has two modes of operation: bistable and chaotic, and switching between these two modes is conveniently achieved by setting a mode-control bit (at a secret position) in an applied input challenge. We exemplify our PUF design framework for two different PUF variants - the CMOS Arbiter PUF and a previously proposed hybrid CMOS-memristor PUF, combined with a hardware realization of the Lorenz system as the chaotic component. Through detailed circuit simulation and modeling attack experiments, we demonstrate that the proposed PUF circuits are highly robust to modeling and cryptanalytic attacks, without degrading the reliability of the original PUF that was combined with the chaotic circuit, and incurs acceptable hardware footprint.
KW - Chaotic PUF
KW - hardware security
KW - Lorenz chaotic system
KW - machine learning-based modeling attack
KW - memristor
KW - physically unclonable function (PUF)
UR - http://www.scopus.com/inward/record.url?scp=85122625228&partnerID=8YFLogxK
U2 - 10.1145/3460004
DO - 10.1145/3460004
M3 - Article
AN - SCOPUS:85122625228
SN - 1084-4309
VL - 26
JO - ACM transactions on design automation of electronic systems
JF - ACM transactions on design automation of electronic systems
IS - 6
M1 - 3460004
ER -