A Dependability Solution for Homogeneous MPSoCs

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    Nowadays highly dependable electronic devices are demanded by many safety-critical applications. Dependability attributes such as reliability and availability/maintainability of a many-processor system-on-chip (MPSoC) should already be examined at the design phase. Design for dependability approaches such as using available fault-free processor-cores and introducing a dependability manager infrastructural IP for self- test and evaluation can greatly enhance the dependability of an MPSoC. This is further supported by subsequent software-based repair. Design choices such as test fault coverage, test and repair time are examined to optimize the dependability attributes. Utilizing existing infrastructures like a network-on-chip (NoC) and tile-wrappers are needed to ensure a test can be performed at application run-time. An example design following the proposed design for dependability approach is shown. The MPSoC has been processed and measurement results have validated the proposed dependability approach.
    Original languageUndefined
    Title of host publication17th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2011
    EditorsXiao Zhang, X. Zhang
    Place of PublicationUSA
    PublisherIEEE Computer Society
    Number of pages10
    ISBN (Print)978-0-7695-4590-5
    Publication statusPublished - 12 Dec 2011

    Publication series

    PublisherIEEE Computer Society
    ISSN (Print)1082-3409


    • METIS-281659
    • MP-SoC
    • IR-78996
    • Availability
    • Reliability
    • NoC (TAM)
    • self-repair
    • Dependability
    • self-test
    • EWI-21032
    • EC Grant Agreement nr.: FP7/215881
    • Fault Tolerance

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