Nowadays highly dependable electronic devices are demanded by many safety-critical applications. Dependability attributes such as reliability and availability/maintainability of a many-processor system-on-chip (MPSoC) should already be examined at the design phase. Design for dependability approaches such as using available fault-free processor-cores and introducing a dependability manager infrastructural IP for self- test and evaluation can greatly enhance the dependability of an MPSoC. This is further supported by subsequent software-based repair. Design choices such as test fault coverage, test and repair time are examined to optimize the dependability attributes. Utilizing existing infrastructures like a network-on-chip (NoC) and tile-wrappers are needed to ensure a test can be performed at application run-time. An example design following the proposed design for dependability approach is shown. The MPSoC has been processed and measurement results have validated the proposed dependability approach.
|Publisher||IEEE Computer Society|
|Conference||17th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2011|
|Period||12/12/11 → 14/12/11|
|Other||12-14 December 2011|
- NoC (TAM)
- EC Grant Agreement nr.: FP7/215881
- Fault Tolerance