A design for testability expert system for silicon compilers

R.P. van Riessen, R.P. van Riessen, Hans G. Kerkhoff, J.M.J. Janssen

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    This paper describes a design-for-testability expert system for the selection of the most appropriate test method for every macro within an IC. The interface with the system designer is user-friendly and together with an efficient search mechanism this expert system can be used as a framework for all types of macros. This tool will be used in a self-test compiler, which generates the layout of self-testable macros automatically. The self-test compiler can be part of a silicon compilation system and thus contribute to the integration of testability into the design process
    Original languageUndefined
    Title of host publicationProceedings 9th Anual IEEE VLSI Test Symposium
    Place of PublicationAtlantic City
    Number of pages0
    Publication statusPublished - 1 Apr 1991
    EventVLSI Test Symposium, VTS 1991 - Atlantic City, United States
    Duration: 15 Apr 199117 Apr 1991

    Publication series



    ConferenceVLSI Test Symposium, VTS 1991
    Abbreviated titleVTS
    Country/TerritoryUnited States
    CityAtlantic City


    • METIS-112968
    • IR-16084

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