A Digital Sine-Weighted switched-Gm mixer for Single-Clock Power-Scalable parallel receivers

Reda Kasri, Eric A.M. Klumperink, Philippe Cathelin, Eric Tournier, Bram Nauta

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    3 Citations (Scopus)
    83 Downloads (Pure)

    Abstract

    Abstract— This paper presents a mixed A/D architecture for parallel channelized RF receiver applications. Its power consumption scales with the number of active receivers and hence with the available overall data rate. A digital sine-weighted
    switched-Gm mixer with a DDFS per channel is proposed as a zero-IF mixer. The DDFS of all channels are programmable via a Look up Table and are driven by a single central clock. Each channel also exploits a 2-path filter to increase selectivity and interference robustness. To demonstrate the concept two parallel
    receivers were implemented in a 28nm UTBB FD-SOI CMOS, with 9.5mW/receiver, achieving 40dB of dynamic range, 13dB NFand better than 75 dB inter-receiver isolation.
    Original languageEnglish
    Title of host publication2017 IEEE Custom Integrated Circuits Conference (CICC)
    PublisherIEEE
    Number of pages4
    ISBN (Electronic)978-1-5090-5191-5
    ISBN (Print)978-1-5090-5192-2
    DOIs
    Publication statusPublished - 3 May 2017
    EventIEEE Custom Integrated Circuits Conference 2017, CICC - Van Zandt Hotel, Austin, United States
    Duration: 30 Apr 20173 May 2017
    http://ieee-cicc.org/2017/

    Conference

    ConferenceIEEE Custom Integrated Circuits Conference 2017, CICC
    Abbreviated titleCICC 2017
    CountryUnited States
    CityAustin
    Period30/04/173/05/17
    Internet address

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  • Cite this

    Kasri, R., Klumperink, E. A. M., Cathelin, P., Tournier, E., & Nauta, B. (2017). A Digital Sine-Weighted switched-Gm mixer for Single-Clock Power-Scalable parallel receivers. In 2017 IEEE Custom Integrated Circuits Conference (CICC) IEEE. https://doi.org/10.1109/CICC.2017.7993644