Abstract
Abstract— This paper presents a mixed A/D architecture for parallel channelized RF receiver applications. Its power consumption scales with the number of active receivers and hence with the available overall data rate. A digital sine-weighted
switched-Gm mixer with a DDFS per channel is proposed as a zero-IF mixer. The DDFS of all channels are programmable via a Look up Table and are driven by a single central clock. Each channel also exploits a 2-path filter to increase selectivity and interference robustness. To demonstrate the concept two parallel
receivers were implemented in a 28nm UTBB FD-SOI CMOS, with 9.5mW/receiver, achieving 40dB of dynamic range, 13dB NFand better than 75 dB inter-receiver isolation.
switched-Gm mixer with a DDFS per channel is proposed as a zero-IF mixer. The DDFS of all channels are programmable via a Look up Table and are driven by a single central clock. Each channel also exploits a 2-path filter to increase selectivity and interference robustness. To demonstrate the concept two parallel
receivers were implemented in a 28nm UTBB FD-SOI CMOS, with 9.5mW/receiver, achieving 40dB of dynamic range, 13dB NFand better than 75 dB inter-receiver isolation.
Original language | English |
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Title of host publication | 2017 IEEE Custom Integrated Circuits Conference (CICC) |
Publisher | IEEE |
Number of pages | 4 |
ISBN (Electronic) | 978-1-5090-5191-5 |
ISBN (Print) | 978-1-5090-5192-2 |
DOIs | |
Publication status | Published - 3 May 2017 |
Event | IEEE Custom Integrated Circuits Conference 2017, CICC - Van Zandt Hotel, Austin, United States Duration: 30 Apr 2017 → 3 May 2017 http://ieee-cicc.org/2017/ |
Conference
Conference | IEEE Custom Integrated Circuits Conference 2017, CICC |
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Abbreviated title | CICC 2017 |
Country/Territory | United States |
City | Austin |
Period | 30/04/17 → 3/05/17 |
Internet address |