A Digital Sine-Weighted switched-Gm mixer for Single-Clock Power-Scalable parallel receivers

Reda Kasri; Eric A.M. Klumperink; Philippe Cathelin; Eric Tournier; Bram  Nauta

doi:10.1109/CICC.2017.7993644

A Digital Sine-Weighted switched-Gm mixer for Single-Clock Power-Scalable parallel receivers

Reda Kasri
, Eric A.M. Klumperink
, Philippe Cathelin
, Eric Tournier
, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

5 Citations (Scopus)

376 Downloads (Pure)

Abstract

Abstract— This paper presents a mixed A/D architecture for parallel channelized RF receiver applications. Its power consumption scales with the number of active receivers and hence with the available overall data rate. A digital sine-weighted
switched-Gm mixer with a DDFS per channel is proposed as a zero-IF mixer. The DDFS of all channels are programmable via a Look up Table and are driven by a single central clock. Each channel also exploits a 2-path filter to increase selectivity and interference robustness. To demonstrate the concept two parallel
receivers were implemented in a 28nm UTBB FD-SOI CMOS, with 9.5mW/receiver, achieving 40dB of dynamic range, 13dB NFand better than 75 dB inter-receiver isolation.

Original language	English
Title of host publication	2017 IEEE Custom Integrated Circuits Conference (CICC)
Publisher	IEEE
Number of pages	4
ISBN (Electronic)	978-1-5090-5191-5
ISBN (Print)	978-1-5090-5192-2
DOIs	https://doi.org/10.1109/CICC.2017.7993644
Publication status	Published - 3 May 2017
Event	IEEE Custom Integrated Circuits Conference 2017, CICC - Van Zandt Hotel, Austin, United States Duration: 30 Apr 2017 → 3 May 2017 http://ieee-cicc.org/2017/

Conference

Conference	IEEE Custom Integrated Circuits Conference 2017, CICC
Abbreviated title	CICC 2017
Country/Territory	United States
City	Austin
Period	30/04/17 → 3/05/17
Internet address	http://ieee-cicc.org/2017/

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10.1109/CICC.2017.7993644

CICC 2017 Reda KasriAccepted author version, 2.23 MB

Cite this

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title = "A Digital Sine-Weighted switched-Gm mixer for Single-Clock Power-Scalable parallel receivers",

abstract = "Abstract{\textemdash} This paper presents a mixed A/D architecture for parallel channelized RF receiver applications. Its power consumption scales with the number of active receivers and hence with the available overall data rate. A digital sine-weighted switched-Gm mixer with a DDFS per channel is proposed as a zero-IF mixer. The DDFS of all channels are programmable via a Look up Table and are driven by a single central clock. Each channel also exploits a 2-path filter to increase selectivity and interference robustness. To demonstrate the concept two parallel receivers were implemented in a 28nm UTBB FD-SOI CMOS, with 9.5mW/receiver, achieving 40dB of dynamic range, 13dB NFand better than 75 dB inter-receiver isolation. ",

author = "Reda Kasri and Klumperink, \{Eric A.M.\} and Philippe Cathelin and Eric Tournier and Bram Nauta",

year = "2017",

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doi = "10.1109/CICC.2017.7993644",

language = "English",

isbn = "978-1-5090-5192-2",

booktitle = "2017 IEEE Custom Integrated Circuits Conference (CICC)",

publisher = "IEEE",

address = "United States",

note = "IEEE Custom Integrated Circuits Conference 2017, CICC, CICC 2017 ; Conference date: 30-04-2017 Through 03-05-2017",

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T1 - A Digital Sine-Weighted switched-Gm mixer for Single-Clock Power-Scalable parallel receivers

AU - Kasri, Reda

AU - Klumperink, Eric A.M.

AU - Cathelin, Philippe

AU - Tournier, Eric

AU - Nauta, Bram

PY - 2017/5/3

Y1 - 2017/5/3

N2 - Abstract— This paper presents a mixed A/D architecture for parallel channelized RF receiver applications. Its power consumption scales with the number of active receivers and hence with the available overall data rate. A digital sine-weighted switched-Gm mixer with a DDFS per channel is proposed as a zero-IF mixer. The DDFS of all channels are programmable via a Look up Table and are driven by a single central clock. Each channel also exploits a 2-path filter to increase selectivity and interference robustness. To demonstrate the concept two parallel receivers were implemented in a 28nm UTBB FD-SOI CMOS, with 9.5mW/receiver, achieving 40dB of dynamic range, 13dB NFand better than 75 dB inter-receiver isolation.

AB - Abstract— This paper presents a mixed A/D architecture for parallel channelized RF receiver applications. Its power consumption scales with the number of active receivers and hence with the available overall data rate. A digital sine-weighted switched-Gm mixer with a DDFS per channel is proposed as a zero-IF mixer. The DDFS of all channels are programmable via a Look up Table and are driven by a single central clock. Each channel also exploits a 2-path filter to increase selectivity and interference robustness. To demonstrate the concept two parallel receivers were implemented in a 28nm UTBB FD-SOI CMOS, with 9.5mW/receiver, achieving 40dB of dynamic range, 13dB NFand better than 75 dB inter-receiver isolation.

U2 - 10.1109/CICC.2017.7993644

DO - 10.1109/CICC.2017.7993644

M3 - Conference contribution

SN - 978-1-5090-5192-2

BT - 2017 IEEE Custom Integrated Circuits Conference (CICC)

PB - IEEE

T2 - IEEE Custom Integrated Circuits Conference 2017, CICC

Y2 - 30 April 2017 through 3 May 2017

ER -

A Digital Sine-Weighted switched-Gm mixer for Single-Clock Power-Scalable parallel receivers

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