A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic Rejection

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    Abstract

    A discrete-time mixing architecture for software-defined radio receivers exploits 8 RF voltage oversampling followed by charge-domain weighting to achieve 40dB 3rd and 5th harmonic rejection without channel bandwidth limitations. Noise folding is also reduced by 3dB. A zero-IF downconverter chip in 65nm CMOS can receive RF signals up to 900MHz, with NFmin=12dB, IIP3=11dBm at <20mW power consumption including multi-phase clock generation.
    Original languageEnglish
    Title of host publicationProceedings of the IEEE International Solid-State Circuits Conference (ISSCC)
    Place of PublicationPiscataway
    PublisherIEEE Computer Society Press
    Pages322-323+616
    Number of pages3
    ISBN (Print)978-1-4244-2011-7
    DOIs
    Publication statusPublished - 6 Feb 2008
    EventIEEE International Solid- State Circuits Conference, ISSCC 2008 - San Francisco, United States
    Duration: 3 Feb 20087 Feb 2008

    Publication series

    Name
    PublisherIEEE Computer Society Press
    NumberDTR08-9

    Conference

    ConferenceIEEE International Solid- State Circuits Conference, ISSCC 2008
    Abbreviated titleISSCC
    CountryUnited States
    CitySan Francisco
    Period3/02/087/02/08

    Keywords

    • EWI-13061
    • IR-62387
    • METIS-251080

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