A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic Rejection

Z. Ru; Eric A.M. Klumperink; Bram Nauta

doi:10.1109/ISSCC.2008.4523187

A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic Rejection

Z. Ru, Eric A.M. Klumperink, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

33 Citations (Scopus)

232 Downloads (Pure)

Abstract

A discrete-time mixing architecture for software-defined radio receivers exploits 8 RF voltage oversampling followed by charge-domain weighting to achieve 40dB 3rd and 5th harmonic rejection without channel bandwidth limitations. Noise folding is also reduced by 3dB. A zero-IF downconverter chip in 65nm CMOS can receive RF signals up to 900MHz, with NFmin=12dB, IIP3=11dBm at <20mW power consumption including multi-phase clock generation.

Original language	English
Title of host publication	Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC)
Place of Publication	Piscataway
Publisher	IEEE
Pages	322-323+616
Number of pages	3
ISBN (Print)	978-1-4244-2011-7
DOIs	https://doi.org/10.1109/ISSCC.2008.4523187
Publication status	Published - 6 Feb 2008
Event	IEEE International Solid- State Circuits Conference, ISSCC 2008 - San Francisco, United States Duration: 3 Feb 2008 → 7 Feb 2008

Publication series

Name
Publisher	IEEE Computer Society Press
Number	DTR08-9

Conference

Conference	IEEE International Solid- State Circuits Conference, ISSCC 2008
Abbreviated title	ISSCC
Country/Territory	United States
City	San Francisco
Period	3/02/08 → 7/02/08

Keywords

EWI-13061
IR-62387
METIS-251080

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10.1109/ISSCC.2008.4523187

Ru_IEEE_ISSCC_2008Final published version, 707 KB

Cite this

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title = "A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic Rejection",

abstract = "A discrete-time mixing architecture for software-defined radio receivers exploits 8 RF voltage oversampling followed by charge-domain weighting to achieve 40dB 3rd and 5th harmonic rejection without channel bandwidth limitations. Noise folding is also reduced by 3dB. A zero-IF downconverter chip in 65nm CMOS can receive RF signals up to 900MHz, with NFmin=12dB, IIP3=11dBm at <20mW power consumption including multi-phase clock generation.",

keywords = "EWI-13061, IR-62387, METIS-251080",

author = "Z. Ru and Klumperink, {Eric A.M.} and Bram Nauta",

note = "10.1109/ISSCC.2008.4523187 ; IEEE International Solid- State Circuits Conference, ISSCC 2008, ISSCC ; Conference date: 03-02-2008 Through 07-02-2008",

year = "2008",

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language = "English",

isbn = "978-1-4244-2011-7",

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Ru, Z, Klumperink, EAM & Nauta, B 2008, A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic Rejection. in Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC)., 10.1109/ISSCC.2008.4523187, IEEE, Piscataway, pp. 322-323+616, IEEE International Solid- State Circuits Conference, ISSCC 2008, San Francisco, California, United States, 3/02/08. https://doi.org/10.1109/ISSCC.2008.4523187

A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic Rejection. / Ru, Z.; Klumperink, Eric A.M.; Nauta, Bram.
Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC). Piscataway: IEEE, 2008. p. 322-323+616 10.1109/ISSCC.2008.4523187.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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KW - METIS-251080

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Y2 - 3 February 2008 through 7 February 2008

ER -

A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic Rejection

Abstract

Publication series

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Keywords

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