A discrete-time mixing architecture for software-defined radio receivers exploits 8 RF voltage oversampling followed by charge-domain weighting to achieve 40dB 3rd and 5th harmonic rejection without channel bandwidth limitations. Noise folding is also reduced by 3dB. A zero-IF downconverter chip in 65nm CMOS can receive RF signals up to 900MHz, with NFmin=12dB, IIP3=11dBm at <20mW power consumption including multi-phase clock generation.
|Publisher||IEEE Computer Society Press|
|Conference||IEEE International Solid- State Circuits Conference, ISSCC 2008|
|Period||3/02/08 → 7/02/08|