A Discrete-Time Mixing Receiver Architecture with Wideband Image and Harmonic Rejection for Software-Defined Radio

Z. Ru; Eric A.M. Klumperink; Bram Nauta

A Discrete-Time Mixing Receiver Architecture with Wideband Image and Harmonic Rejection for Software-Defined Radio

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

A discrete-time mixing architecture for software defined radio receivers is proposed. It exploits 8x RF voltage oversampling followed by charge domain weighting to achieve 40dB 3rd and 5th harmonic rejection without channel bandwidth limitations. Also noise folding is reduced by 3dB. A zero-IF downconverter chip in 65nm CMOS can receive RF signals up to 900MHz, with NFmin=12dB, IIP3=11dBm at <20mW power consumption including multi-phase clock generation.

Original language	Undefined
Title of host publication	Proceedings of the 19th Annual Workshop on Circuits
Place of Publication	Veldhoven
Publisher	STW
Pages	233-238
Number of pages	6
ISBN (Print)	978-90-73461-56-7
Publication status	Published - 27 Nov 2008
Event	19th Annual Workshop on Circuits, Systems and Signal Processing, ProRISC 2008 - Veldhoven, Netherlands Duration: 27 Nov 2008 → 28 Nov 2008 Conference number: 19

Publication series

Name
Publisher	Technology Foundation STW
Number	412

Conference

Conference	19th Annual Workshop on Circuits, Systems and Signal Processing, ProRISC 2008
Country/Territory	Netherlands
City	Veldhoven
Period	27/11/08 → 28/11/08

Keywords

EWI-14986
METIS-255470
IR-65352

Access to Document

Ru_ProRISC_2008Final published version, 292 KB

Cite this

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title = "A Discrete-Time Mixing Receiver Architecture with Wideband Image and Harmonic Rejection for Software-Defined Radio",

abstract = "A discrete-time mixing architecture for software defined radio receivers is proposed. It exploits 8x RF voltage oversampling followed by charge domain weighting to achieve 40dB 3rd and 5th harmonic rejection without channel bandwidth limitations. Also noise folding is reduced by 3dB. A zero-IF downconverter chip in 65nm CMOS can receive RF signals up to 900MHz, with NFmin=12dB, IIP3=11dBm at <20mW power consumption including multi-phase clock generation.",

keywords = "EWI-14986, METIS-255470, IR-65352",

author = "Z. Ru and Klumperink, {Eric A.M.} and Bram Nauta",

year = "2008",

month = nov,

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language = "Undefined",

isbn = "978-90-73461-56-7",

publisher = "STW",

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AU - Ru, Z.

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N2 - A discrete-time mixing architecture for software defined radio receivers is proposed. It exploits 8x RF voltage oversampling followed by charge domain weighting to achieve 40dB 3rd and 5th harmonic rejection without channel bandwidth limitations. Also noise folding is reduced by 3dB. A zero-IF downconverter chip in 65nm CMOS can receive RF signals up to 900MHz, with NFmin=12dB, IIP3=11dBm at <20mW power consumption including multi-phase clock generation.

AB - A discrete-time mixing architecture for software defined radio receivers is proposed. It exploits 8x RF voltage oversampling followed by charge domain weighting to achieve 40dB 3rd and 5th harmonic rejection without channel bandwidth limitations. Also noise folding is reduced by 3dB. A zero-IF downconverter chip in 65nm CMOS can receive RF signals up to 900MHz, with NFmin=12dB, IIP3=11dBm at <20mW power consumption including multi-phase clock generation.

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KW - METIS-255470

KW - IR-65352

M3 - Conference contribution

SN - 978-90-73461-56-7

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BT - Proceedings of the 19th Annual Workshop on Circuits

PB - STW

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T2 - 19th Annual Workshop on Circuits, Systems and Signal Processing, ProRISC 2008

Y2 - 27 November 2008 through 28 November 2008

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