A Discrete-Time Mixing Receiver Architecture with Wideband Image and Harmonic Rejection for Software-Defined Radio

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    Abstract

    A discrete-time mixing architecture for software defined radio receivers is proposed. It exploits 8x RF voltage oversampling followed by charge domain weighting to achieve 40dB 3rd and 5th harmonic rejection without channel bandwidth limitations. Also noise folding is reduced by 3dB. A zero-IF downconverter chip in 65nm CMOS can receive RF signals up to 900MHz, with NFmin=12dB, IIP3=11dBm at <20mW power consumption including multi-phase clock generation.
    Original languageUndefined
    Title of host publicationProceedings of the 19th Annual Workshop on Circuits
    Place of PublicationVeldhoven
    PublisherSTW
    Pages233-238
    Number of pages6
    ISBN (Print)978-90-73461-56-7
    Publication statusPublished - 27 Nov 2008
    Event19th Annual Workshop on Circuits, Systems and Signal Processing, ProRISC 2008 - Veldhoven, Netherlands
    Duration: 27 Nov 200828 Nov 2008
    Conference number: 19

    Publication series

    Name
    PublisherTechnology Foundation STW
    Number412

    Conference

    Conference19th Annual Workshop on Circuits, Systems and Signal Processing, ProRISC 2008
    CountryNetherlands
    CityVeldhoven
    Period27/11/0828/11/08

    Keywords

    • EWI-14986
    • METIS-255470
    • IR-65352

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