TY - JOUR
T1 - A Double Error Correction Code for 32-Bit Data Words With Efficent Decoding
AU - Liu, Shanshan
AU - Li, Jiaqiang
AU - Reviriego, P.
AU - Ottavi, M.
AU - Xiao, L.
PY - 2018
Y1 - 2018
N2 - There has been recent interest on designing double error correction (DEC) codes for 32-bit data words that support fast decoding as they can be useful to protect memories. To that end, solutions based on orthogonal Latin square codes have been recently presented that achieve fast decoding but require a large number of parity check bits. In this letter, a DEC code derived from difference set codes is presented. The proposed code is able to reduce the number of parity check bits needed at the cost of a slightly more complex decoding. Therefore, it provides memory designers with an additional option that can be useful when making trade-offs between memory size and speed.
AB - There has been recent interest on designing double error correction (DEC) codes for 32-bit data words that support fast decoding as they can be useful to protect memories. To that end, solutions based on orthogonal Latin square codes have been recently presented that achieve fast decoding but require a large number of parity check bits. In this letter, a DEC code derived from difference set codes is presented. The proposed code is able to reduce the number of parity check bits needed at the cost of a slightly more complex decoding. Therefore, it provides memory designers with an additional option that can be useful when making trade-offs between memory size and speed.
UR - http://www.scopus.com/inward/record.url?eid=2-s2.0-85040622721&partnerID=MN8TOARS
U2 - 10.1109/TDMR.2017.2788144
DO - 10.1109/TDMR.2017.2788144
M3 - Article
SN - 1530-4388
VL - 18
SP - 125
EP - 127
JO - IEEE transactions on device and materials reliability
JF - IEEE transactions on device and materials reliability
IS - 1
ER -