A Dual-Alternating-Slope Digital-to-Time Converter Leveraging Mismatch to Improve Delay Step Size

This article introduces a dual-alternating-slope digital-to-time converter (DASDTC) topology that reduces the dependency of DTC delay on component values and power supply. A power-and area-efficient resolution extension method is proposed that benefits from mismatch upon applying a measurement-based code-mapping. Fabricated in GlobalFoundries 22-nm fully depleted silicon-on-insulator (FDSOI) process, the DTC obtains a fine-delay resolution of 0.3 ps in a 180-ps delay window. Combined with a counter-based coarse-delay steps, a wide delay range of 4 ns at an output frequency of 83.3 MHz is obtained. The measured integral non-linearity (INL) of the DTC is below 0.26 ps across four samples. The DTC showcases immunity to supply noise and a figure of merit (FoM) of 3.3 fJ/conversion which is competitive with the current state-of-the-art DTCs.