A fault-tolerant 176 Gbit Solid State Mass Memory architecture

G.C. Cardarilli, P. Marinucci, M. Ottavi, A. Salsano

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

5 Citations (Scopus)


This paper presents a new Solid State Mass Memory (SSMM) suitable for space applications. The memory reliability is increased by using two different approaches. Firstly, memory mass fault-tolerance, with respect to hard failures, is obtained by using a fine-granularity hierarchical structure with a certain level of redundancy. A second strategy used for facing soft errors is based on Error Correction Codes (ECC) and periodic memory washing. A performance index has been developed for evaluating the main parameters of the SSMM architecture. This index takes into account the ECC capability, the memory weight and reliability, allowing to relate them to the required overhead.
Original languageEnglish
Title of host publicationProceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 25-27 October 2000, Yamanashi, Japan
Place of PublicationLos Alamitos, California
Number of pages8
ISBN (Print)0-7695-0719-0
Publication statusPublished - 2000
Externally publishedYes


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