Abstract
In this paper the hardware implementation of a file system manager for a fault tolerant Solid State Mass Memory (SSMM) is presented. A hardware implementation of the file system manager implies the following advantages: ad hoc fault tolerant design and graceful degradation capability. The former means developing special fault tolerant hardware for each file system basic function (read, write and delete). For each function different fault tolerant techniques have been applied by considering the impact of different faults on the architecture reliability. Also the area overhead introduced by the chosen fault tolerant technique has been evaluated. Graceful degradation is obtained in terms of data connection reconfiguration and reduced functionality set. We exploited the modularity of the design to implement a distributed file system by means of local handlers on each memory module connected to a dynamic routing module. The file system manager has been used in a SSMM oriented to satellite applications. An FPGA implementation for the complete SSMM has been obtained in order to evaluate the performances and reliability of the SSMM architecture and in particular of the file system manager.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 2003 International Symposium on Circuits and Systems, 2003, ISCAS '03 |
| Place of Publication | Piscataway, NJ |
| Publisher | IEEE |
| Pages | V-649 - V-652 |
| Number of pages | 4 |
| ISBN (Print) | 0-7803-7761-3 |
| DOIs | |
| Publication status | Published - 2003 |
| Externally published | Yes |
| Event | IEEE International Symposium on Circuits and Systems, ISCAS 2003 - Imperial Queen's Park Hotel, Bangkok, Thailand Duration: 25 May 2003 → 28 May 2003 |
Conference
| Conference | IEEE International Symposium on Circuits and Systems, ISCAS 2003 |
|---|---|
| Abbreviated title | ISCAS '03 |
| Country/Territory | Thailand |
| City | Bangkok |
| Period | 25/05/03 → 28/05/03 |