A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law I-V characteristics of the MOS transistor. Linearity is better then 0.14 % for an output swing of 36 % of the supply current. The bandwidth is from de to above 1 MHz.
|Publication status||Published - 1985|
|Event||11th European Solid-State Circuits Conference, ESSCIRC 1985 - Toulouse, France|
Duration: 16 Sep 1985 → 18 Sep 1985
Conference number: 11
|Conference||11th European Solid-State Circuits Conference, ESSCIRC 1985|
|Period||16/09/85 → 18/09/85|