A four-quadrant CMOS analog multiplier

Klaas Bult; Hans Wallinga

doi:10.1109/ESSCIRC.1985.5468126

A four-quadrant CMOS analog multiplier

Klaas Bult, Hans Wallinga

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Abstract

A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law I-V characteristics of the MOS transistor. Linearity is better then 0.14 % for an output swing of 36 % of the supply current. The bandwidth is from de to above 1 MHz.

Original language	English
Pages	296-301
DOIs	https://doi.org/10.1109/ESSCIRC.1985.5468126
Publication status	Published - 1985
Event	11th European Solid-State Circuits Conference, ESSCIRC 1985 - Toulouse, France Duration: 16 Sept 1985 → 18 Sept 1985 Conference number: 11

Conference

Conference	11th European Solid-State Circuits Conference, ESSCIRC 1985
Abbreviated title	ESSCIRC
Country/Territory	France
City	Toulouse
Period	16/09/85 → 18/09/85

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10.1109/ESSCIRC.1985.5468126

Bult1985four-quadrantFinal published version, 1.62 MB

Cite this

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title = "A four-quadrant CMOS analog multiplier",

abstract = "A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law I-V characteristics of the MOS transistor. Linearity is better then 0.14 % for an output swing of 36 % of the supply current. The bandwidth is from de to above 1 MHz.",

author = "Klaas Bult and Hans Wallinga",

year = "1985",

doi = "10.1109/ESSCIRC.1985.5468126",

language = "English",

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AU - Bult, Klaas

AU - Wallinga, Hans

N1 - Conference code: 11

PY - 1985

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N2 - A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law I-V characteristics of the MOS transistor. Linearity is better then 0.14 % for an output swing of 36 % of the supply current. The bandwidth is from de to above 1 MHz.

AB - A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law I-V characteristics of the MOS transistor. Linearity is better then 0.14 % for an output swing of 36 % of the supply current. The bandwidth is from de to above 1 MHz.

U2 - 10.1109/ESSCIRC.1985.5468126

DO - 10.1109/ESSCIRC.1985.5468126

M3 - Paper

SP - 296

EP - 301

T2 - 11th European Solid-State Circuits Conference, ESSCIRC 1985

Y2 - 16 September 1985 through 18 September 1985

ER -

A four-quadrant CMOS analog multiplier

Abstract

Conference

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Cite this