A four-quadrant CMOS analog multiplier

Klaas Bult, Hans Wallinga

    Research output: Contribution to conferencePaper

    120 Citations (Scopus)
    29 Downloads (Pure)


    A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law I-V characteristics of the MOS transistor. Linearity is better then 0.14 % for an output swing of 36 % of the supply current. The bandwidth is from de to above 1 MHz.
    Original languageEnglish
    Publication statusPublished - 1985
    Event11th European Solid-State Circuits Conference, ESSCIRC 1985 - Toulouse, France
    Duration: 16 Sep 198518 Sep 1985
    Conference number: 11


    Conference11th European Solid-State Circuits Conference, ESSCIRC 1985
    Abbreviated titleESSCIRC

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    Bult, K., & Wallinga, H. (1985). A four-quadrant CMOS analog multiplier. 296-301. Paper presented at 11th European Solid-State Circuits Conference, ESSCIRC 1985, Toulouse, France. https://doi.org/10.1109/ESSCIRC.1985.5468126