A four-quadrant CMOS analog multiplier

Klaas Bult, Hans Wallinga

Research output: Contribution to conferencePaperAcademic

120 Citations (Scopus)
15 Downloads (Pure)

Abstract

A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law I-V characteristics of the MOS transistor. Linearity is better then 0.14 % for an output swing of 36 % of the supply current. The bandwidth is from de to above 1 MHz.
Original languageUndefined
Pages296-301
Publication statusPublished - 1985
Event11th European Solid-State Circuits Conference, ESSCIRC 1985 - Toulouse, France
Duration: 16 Sep 198518 Sep 1985
Conference number: 11

Conference

Conference11th European Solid-State Circuits Conference, ESSCIRC 1985
Abbreviated titleESSCIRC
CountryFrance
CityToulouse
Period16/09/8518/09/85

Keywords

  • IR-96389

Cite this

Bult, K., & Wallinga, H. (1985). A four-quadrant CMOS analog multiplier. 296-301. Paper presented at 11th European Solid-State Circuits Conference, ESSCIRC 1985, Toulouse, France.
Bult, Klaas ; Wallinga, Hans. / A four-quadrant CMOS analog multiplier. Paper presented at 11th European Solid-State Circuits Conference, ESSCIRC 1985, Toulouse, France.
@conference{1af2c989c9bf481bab4520d6fc829d76,
title = "A four-quadrant CMOS analog multiplier",
abstract = "A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law I-V characteristics of the MOS transistor. Linearity is better then 0.14 {\%} for an output swing of 36 {\%} of the supply current. The bandwidth is from de to above 1 MHz.",
keywords = "IR-96389",
author = "Klaas Bult and Hans Wallinga",
year = "1985",
language = "Undefined",
pages = "296--301",
note = "null ; Conference date: 16-09-1985 Through 18-09-1985",

}

Bult, K & Wallinga, H 1985, 'A four-quadrant CMOS analog multiplier' Paper presented at 11th European Solid-State Circuits Conference, ESSCIRC 1985, Toulouse, France, 16/09/85 - 18/09/85, pp. 296-301.

A four-quadrant CMOS analog multiplier. / Bult, Klaas; Wallinga, Hans.

1985. 296-301 Paper presented at 11th European Solid-State Circuits Conference, ESSCIRC 1985, Toulouse, France.

Research output: Contribution to conferencePaperAcademic

TY - CONF

T1 - A four-quadrant CMOS analog multiplier

AU - Bult, Klaas

AU - Wallinga, Hans

PY - 1985

Y1 - 1985

N2 - A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law I-V characteristics of the MOS transistor. Linearity is better then 0.14 % for an output swing of 36 % of the supply current. The bandwidth is from de to above 1 MHz.

AB - A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law I-V characteristics of the MOS transistor. Linearity is better then 0.14 % for an output swing of 36 % of the supply current. The bandwidth is from de to above 1 MHz.

KW - IR-96389

M3 - Paper

SP - 296

EP - 301

ER -

Bult K, Wallinga H. A four-quadrant CMOS analog multiplier. 1985. Paper presented at 11th European Solid-State Circuits Conference, ESSCIRC 1985, Toulouse, France.