A new front-end for a pixel detector readout chip was designed. A non-standard topology was used to achieve low noise and fast return to zero of the preamplifier to be immune to pile-up of subsequent input signals. This front-end has been implemented on a pixel detector readout chip developed in a commercial 0.25 μm CMOS technology for the ALICE and LHCb experiments. This technology proved to be radiation tolerant when special layout techniques are used, and provides sufficient density for these applications. The chip is a matrix of 32 columns each containing 256 readout cells. Each readout cell comprises this front-end and digital readout circuitry, and has a static power consumption of about 60 μW.