A genetic algorithm based remaining lifetime prediction for a VLIW processor employing path delay and IDDX testing

Hans G. Kerkhoff

doi:10.1109/DTIS.2016.7483805

A genetic algorithm based remaining lifetime prediction for a VLIW processor employing path delay and IDDX testing

Hans G. Kerkhoff

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

9 Citations (Scopus)

5 Downloads (Pure)

Abstract

In this paper, critical path-delay time, and quiescent and transient power-supply current testing have been applied to a 90nm VLIW processor, to predict the remaining lifetime of this processor. The test environment for validation, via implementing an accelerated test has been realized. The resulting delay and current measurement data is presented next, followed by applying a genetic algorithm (GA) to construct a lifetime prediction model for the processor. The calculated remaining lifetime predicted by power-supply testing is close to that of delay-time testing.

Original language	Undefined
Title of host publication	International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2016
Editors	Yong Zhao
Place of Publication	Piscataway, NJ, USA
Publisher	IEEE
Pages	10-14
Number of pages	4
ISBN (Print)	978-1-5090-0336-5
DOIs	https://doi.org/10.1109/DTIS.2016.7483805
Publication status	Published - 2 Jun 2016
Event	International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2016 - Istanbul, Turkey Duration: 12 Apr 2016 → 14 Apr 2016

Publication series

Name
Publisher	IEEE Computer Society

Conference

Conference	International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2016
Abbreviated title	DTIS 2016
Country/Territory	Turkey
City	Istanbul
Period	12/04/16 → 14/04/16

Keywords

Aging
Genetic Algorithms
EC Grant Agreement nr.: FP7/619871
Delays
Current measurement
EWI-26387
Temperature measurement
Testing
METIS-318444
IR-101896
Degradation

Access to Document

10.1109/DTIS.2016.7483805

Cite this

@inproceedings{f721bc0e7c7c4977ac8a99549360aced,

title = "A genetic algorithm based remaining lifetime prediction for a VLIW processor employing path delay and IDDX testing",

abstract = "In this paper, critical path-delay time, and quiescent and transient power-supply current testing have been applied to a 90nm VLIW processor, to predict the remaining lifetime of this processor. The test environment for validation, via implementing an accelerated test has been realized. The resulting delay and current measurement data is presented next, followed by applying a genetic algorithm (GA) to construct a lifetime prediction model for the processor. The calculated remaining lifetime predicted by power-supply testing is close to that of delay-time testing.",

keywords = "Aging, Genetic Algorithms, EC Grant Agreement nr.: FP7/619871, Delays, Current measurement, EWI-26387, Temperature measurement, Testing, METIS-318444, IR-101896, Degradation",

author = "Kerkhoff, {Hans G.}",

note = "eemcs-eprint-26387 ; null ; Conference date: 12-04-2016 Through 14-04-2016",

year = "2016",

month = jun,

day = "2",

doi = "10.1109/DTIS.2016.7483805",

language = "Undefined",

isbn = "978-1-5090-0336-5",

publisher = "IEEE",

pages = "10--14",

editor = "Yong Zhao",

booktitle = "International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2016",

}

Kerkhoff, HG 2016, A genetic algorithm based remaining lifetime prediction for a VLIW processor employing path delay and IDDX testing. in Y Zhao (ed.), International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2016. IEEE, Piscataway, NJ, USA, pp. 10-14, International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2016, Istanbul, Turkey, 12/04/16. https://doi.org/10.1109/DTIS.2016.7483805

A genetic algorithm based remaining lifetime prediction for a VLIW processor employing path delay and IDDX testing. / Kerkhoff, Hans G.

International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2016. ed. / Yong Zhao. Piscataway, NJ, USA : IEEE, 2016. p. 10-14.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A genetic algorithm based remaining lifetime prediction for a VLIW processor employing path delay and IDDX testing

AU - Kerkhoff, Hans G.

N1 - eemcs-eprint-26387

PY - 2016/6/2

Y1 - 2016/6/2

N2 - In this paper, critical path-delay time, and quiescent and transient power-supply current testing have been applied to a 90nm VLIW processor, to predict the remaining lifetime of this processor. The test environment for validation, via implementing an accelerated test has been realized. The resulting delay and current measurement data is presented next, followed by applying a genetic algorithm (GA) to construct a lifetime prediction model for the processor. The calculated remaining lifetime predicted by power-supply testing is close to that of delay-time testing.

AB - In this paper, critical path-delay time, and quiescent and transient power-supply current testing have been applied to a 90nm VLIW processor, to predict the remaining lifetime of this processor. The test environment for validation, via implementing an accelerated test has been realized. The resulting delay and current measurement data is presented next, followed by applying a genetic algorithm (GA) to construct a lifetime prediction model for the processor. The calculated remaining lifetime predicted by power-supply testing is close to that of delay-time testing.

KW - Aging

KW - Genetic Algorithms

KW - EC Grant Agreement nr.: FP7/619871

KW - Delays

KW - Current measurement

KW - EWI-26387

KW - Temperature measurement

KW - Testing

KW - METIS-318444

KW - IR-101896

KW - Degradation

U2 - 10.1109/DTIS.2016.7483805

DO - 10.1109/DTIS.2016.7483805

M3 - Conference contribution

SN - 978-1-5090-0336-5

SP - 10

EP - 14

BT - International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2016

A2 - Zhao, Yong

PB - IEEE

CY - Piscataway, NJ, USA

Y2 - 12 April 2016 through 14 April 2016

ER -