A genetic algorithm based remaining lifetime prediction for a VLIW processor employing path delay and IDDX testing

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    Abstract

    In this paper, critical path-delay time, and quiescent and transient power-supply current testing have been applied to a 90nm VLIW processor, to predict the remaining lifetime of this processor. The test environment for validation, via implementing an accelerated test has been realized. The resulting delay and current measurement data is presented next, followed by applying a genetic algorithm (GA) to construct a lifetime prediction model for the processor. The calculated remaining lifetime predicted by power-supply testing is close to that of delay-time testing.
    Original languageUndefined
    Title of host publicationInternational Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2016
    EditorsYong Zhao
    Place of PublicationPiscataway, NJ, USA
    PublisherIEEE Computer Society
    Pages10-14
    Number of pages4
    ISBN (Print)978-1-5090-0336-5
    DOIs
    Publication statusPublished - 2 Jun 2016
    EventInternational Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2016 - Istanbul, Turkey
    Duration: 12 Apr 201614 Apr 2016

    Publication series

    Name
    PublisherIEEE Computer Society

    Conference

    ConferenceInternational Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2016
    Period12/04/1614/04/16
    Other12-14 April 2016

    Keywords

    • Aging
    • Genetic Algorithms
    • EC Grant Agreement nr.: FP7/619871
    • Delays
    • Current measurement
    • EWI-26387
    • Temperature measurement
    • Testing
    • METIS-318444
    • IR-101896
    • Degradation

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