A High-Level Synthesis Tool for the Assignment of Storage Values to Sequential Read-Write memories

Sabih H. Gerez, E.G. Woutersen

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    Original languageUndefined
    Title of host publicationProceedings of the International Workshop on Logic and Architecture Synthesis organized by IFIP TC10 WG10.5
    Place of PublicationGrenoble, France
    Number of pages11
    Publication statusPublished - 18 Dec 1995


    • METIS-113169

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