A high-linearity digital-to-time converter technique: constant-slope charging

Z. Ru, Claudia Palattella, P.F.J. Geraedts, Eric A.M. Klumperink, Bram Nauta

    Research output: Contribution to journalArticleAcademicpeer-review

    38 Citations (Scopus)
    351 Downloads (Pure)

    Abstract

    A digital-to-time converter (DTC) controls time delay by a digital code, which is useful, for example, in a sampling oscilloscope, fractional-N PLL, or time-interleaved ADC. This paper proposes constant-slope charging as a method to realize a DTC with intrinsically better integral non-linearity (INL) compared to the popular variable-slope method. The proposed DTC chip realized in 65 nm CMOS consists of a voltage-controlled variable-delay element (DTC-core) driven by a 10 bit digital-to-analog converter. Measurements with a 55 MHz crystal clock demonstrate a full-scale delay programmable from 19 ps to 189 ps with a resolution from 19 fs to 185 fs. As available oscilloscopes are not good enough to reliably measure such high timing resolution, a frequency-domain method has been developed that modulates a DTC edge and derives INL from spur strength. An INL of 0.17% at 189 ps full-scale delay and 0.34% at 19 ps are measured, representing 8–9 bit effective INL-limited resolution. Output rms jitter is better than 210 fs limited by the test setup, while the DTC consumes 1.8 mW.
    Original languageEnglish
    Pages (from-to)1412-1423
    Number of pages12
    JournalIEEE journal of solid-state circuits
    Volume50
    Issue number6
    DOIs
    Publication statusPublished - 1 Jun 2015

    Keywords

    • METIS-312663
    • EWI-26129
    • IR-96468

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