Abstract
This paper describes the power dissipation analysis
and the design of an efficiency-improved high-voltage class-D power amplifier. The amplifier adaptively regulates its switching frequency for optimal power efficiency across the full output power range. This is based on detecting the switching output node voltage level at the turn-on transition of the power switches. Implemented
in a 0.14 m SOI BCD process, the amplifier achieves
93% efficiency at 45 W output power,80% power efficiency
down to 4.5 W output power and 49% efficiency down to 0.45 W
output power.
Original language | English |
---|---|
Pages (from-to) | 1451-1462 |
Number of pages | 12 |
Journal | IEEE journal of solid-state circuits |
Volume | 50 |
Issue number | 6 |
DOIs | |
Publication status | Published - 1 Jun 2015 |
Keywords
- EWI-26096
- IR-96384
- METIS-312649