A High-Voltage Level Tolerant Transistor Circuit

Anne Johan Annema (Inventor), Godefridus Johannes Gertrudis Maria Geelen (Inventor)

    Research output: Patent

    60 Downloads (Pure)


    A high-voltage level tolerant transistor circuit, comprising a plurality of cascoded transistors, including a first transistor (T1) operatively connected to a high-voltage level node (3) and a second transistor (T2) operatively connected to a low-voltage level node (2). The first transistor (T1) connects to a biasing circuit (8), such as a voltage level shifter, providing a variable biasing level (V1) relative to a voltage level (VH) at the high-voltage level node (3).
    Original languageEnglish
    Patent numberUS6320414B1
    Publication statusPublished - 20 Nov 2001


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