Abstract
A high-voltage level tolerant transistor circuit, comprising a plurality of cascoded transistors, including a first transistor (T1) operatively connected to a high-voltage level node (3) and a second transistor (T2) operatively connected to a low-voltage level node (2). The first transistor (T1) connects to a biasing circuit (8), such as a voltage level shifter, providing a variable biasing level (V1) relative to a voltage level (VH) at the high-voltage level node (3).
| Original language | English |
|---|---|
| Patent number | WO2000070763A1 |
| Priority date | 23/11/00 |
| Publication status | Published - 23 Nov 2000 |