A high-voltage level tolerant transistor circuit

A.J. Annema (Inventor), G.J.G.M. Geelen (Inventor)

Research output: Patent

4 Downloads (Pure)

Abstract

A high-voltage level tolerant transistor circuit, comprising a plurality of cascoded transistors, including a first transistor (T1) operatively connected to a high-voltage level node (3) and a second transistor (T2) operatively connected to a low-voltage level node (2). The first transistor (T1) connects to a biasing circuit (8), such as a voltage level shifter, providing a variable biasing level (V1) relative to a voltage level (VH) at the high-voltage level node (3).
Original languageEnglish
Patent numberWO2000070763A1
Priority date23/11/00
Publication statusPublished - 23 Nov 2000

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