Abstract
A high-voltage level tolerant transistor circuit, comprising a plurality of cascoded transistors, including a first transistor (T1) operatively connected to a high-voltage level node (3) and a second transistor (T2) operatively connected to a low-voltage level node (2). The first transistor (T1) connects to a biasing circuit (8), such as a voltage level shifter, providing a variable biasing level (V1) relative to a voltage level (VH) at the high-voltage level node (3).
| Original language | English |
|---|---|
| Patent number | EP1099306 |
| Priority date | 16/05/01 |
| Publication status | Published - 16 May 2001 |
Fingerprint Dive into the research topics of 'A High-Voltage Level Tolerant Transistor Circuit'. Together they form a unique fingerprint.
Cite this
Annema, A. J., & Geelen, G. J. G. M. (2001). A High-Voltage Level Tolerant Transistor Circuit. (Patent No. EP1099306).