Optimal simulation speed and synthesizability are contradictory requirements for a hardware descrip- tion language. This paper presents a language and toolset that enables both synthesis and fast simulation of fixed- point signal processing algorithms at the register-transfer level using a single system description. This is achieved by separate code generators for different purposes. Code-generators have been developed for fast simulation (using ANSI-C) and for synthesis (using VHDL). The simulation performance of the proposed approach has been compared with other known methods and turns out to be comparable in speed to the fastest among them.
|Title of host publication||ProRISC 2005 16th Annual Workshop on Circuits, Systems and Signal Processing|
|Place of Publication||Utrecht|
|Number of pages||6|
|Publication status||Published - 17 Nov 2005|
|Event||16th Workshop on Circuits, Systems and Signal Processing, ProRISC 2005 - Veldhoven, Netherlands|
Duration: 17 Nov 2005 → 18 Nov 2005
Conference number: 16
|Workshop||16th Workshop on Circuits, Systems and Signal Processing, ProRISC 2005|
|Period||17/11/05 → 18/11/05|
- Hardware Description Languages
Hofstra, K. L., Gerez, S. H., & van Kampen, D. (2005). A Language and Toolset for the Synthesis and Efficient Simulation of Clock-Cycle-True Signal-Processing Algorithms. In ProRISC 2005 16th Annual Workshop on Circuits, Systems and Signal Processing (pp. 518-523). Utrecht: STW.