A Language and Toolset for the Synthesis and Efficient Simulation of Clock-Cycle-True Signal-Processing Algorithms

K.L. Hofstra, Sabih H. Gerez, David van Kampen

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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Abstract

Optimal simulation speed and synthesizability are contradictory requirements for a hardware descrip- tion language. This paper presents a language and toolset that enables both synthesis and fast simulation of fixed- point signal processing algorithms at the register-transfer level using a single system description. This is achieved by separate code generators for different purposes. Code-generators have been developed for fast simulation (using ANSI-C) and for synthesis (using VHDL). The simulation performance of the proposed approach has been compared with other known methods and turns out to be comparable in speed to the fastest among them.
Original languageUndefined
Title of host publicationProRISC 2005 16th Annual Workshop on Circuits, Systems and Signal Processing
Place of PublicationUtrecht
PublisherSTW
Pages518-523
Number of pages6
ISBN (Print)90-73461-50-2
Publication statusPublished - 17 Nov 2005
Event16th Workshop on Circuits, Systems and Signal Processing, ProRISC 2005 - Veldhoven, Netherlands
Duration: 17 Nov 200518 Nov 2005
Conference number: 16

Workshop

Workshop16th Workshop on Circuits, Systems and Signal Processing, ProRISC 2005
CountryNetherlands
CityVeldhoven
Period17/11/0518/11/05

Keywords

  • Hardware Description Languages
  • Simulation
  • IR-59554
  • EWI-13338
  • METIS-226845
  • Synthesis

Cite this

Hofstra, K. L., Gerez, S. H., & van Kampen, D. (2005). A Language and Toolset for the Synthesis and Efficient Simulation of Clock-Cycle-True Signal-Processing Algorithms. In ProRISC 2005 16th Annual Workshop on Circuits, Systems and Signal Processing (pp. 518-523). Utrecht: STW.
Hofstra, K.L. ; Gerez, Sabih H. ; van Kampen, David. / A Language and Toolset for the Synthesis and Efficient Simulation of Clock-Cycle-True Signal-Processing Algorithms. ProRISC 2005 16th Annual Workshop on Circuits, Systems and Signal Processing. Utrecht : STW, 2005. pp. 518-523
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Hofstra, KL, Gerez, SH & van Kampen, D 2005, A Language and Toolset for the Synthesis and Efficient Simulation of Clock-Cycle-True Signal-Processing Algorithms. in ProRISC 2005 16th Annual Workshop on Circuits, Systems and Signal Processing. STW, Utrecht, pp. 518-523, 16th Workshop on Circuits, Systems and Signal Processing, ProRISC 2005, Veldhoven, Netherlands, 17/11/05.

A Language and Toolset for the Synthesis and Efficient Simulation of Clock-Cycle-True Signal-Processing Algorithms. / Hofstra, K.L.; Gerez, Sabih H.; van Kampen, David.

ProRISC 2005 16th Annual Workshop on Circuits, Systems and Signal Processing. Utrecht : STW, 2005. p. 518-523.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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AB - Optimal simulation speed and synthesizability are contradictory requirements for a hardware descrip- tion language. This paper presents a language and toolset that enables both synthesis and fast simulation of fixed- point signal processing algorithms at the register-transfer level using a single system description. This is achieved by separate code generators for different purposes. Code-generators have been developed for fast simulation (using ANSI-C) and for synthesis (using VHDL). The simulation performance of the proposed approach has been compared with other known methods and turns out to be comparable in speed to the fastest among them.

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Hofstra KL, Gerez SH, van Kampen D. A Language and Toolset for the Synthesis and Efficient Simulation of Clock-Cycle-True Signal-Processing Algorithms. In ProRISC 2005 16th Annual Workshop on Circuits, Systems and Signal Processing. Utrecht: STW. 2005. p. 518-523