An architecture is presented for low-cost and flexible realisation of image processing and analysis algorithms of binary images. The flexibility of the architecture is due to reconfigurable network of simple boolean functions. It is shown that this architecture can readily be implemented by low-cost off-the-shelf components. This is illustrated by some simulations of a hypothetical realisation.
|Title of host publication||Proceedings 11th IAPR International Conference on Pattern Recognition|
|Place of Publication||Piscataway, NJ|
|Number of pages||4|
|Publication status||Published - 30 Aug 1992|