A Low-jitter 2.5-to-10 GHz Clock Multiplier Unit in CMOS

R.C.H. van de Beek, C.S. Vaucher, D.M.W. Leenaerts, Eric A.M. Klumperink, Bram Nauta

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    Abstract— This paper demonstrates a low-jitter clock multiplier unit [1] that generates a 10 GHz output clock from a 2.5 GHz reference clock. An integrated 10 GHz LCoscillator is locked to the input clock, using a simple and fast phase detector circuit. This phase detector overcomes the speed limitation of a conventional tri-state Phase Frequency Detector, by eliminating an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18¹m CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8 V supply.
    Original languageUndefined
    Title of host publicationthe 14th ProRisc workshop on Circuits, Systems and Signal Processing (ProRisc 2003)
    Place of PublicationUtrecht
    Number of pages4
    ISBN (Print)90-73461-39-1
    Publication statusPublished - Nov 2003
    Event14th ProRISC Workshop on Circuits, Systems and Signal Processing 2003 - Veldhoven, Netherlands
    Duration: 25 Nov 200327 Nov 2003
    Conference number: 14

    Publication series

    PublisherSTW Technology Foundation


    Workshop14th ProRISC Workshop on Circuits, Systems and Signal Processing 2003
    Abbreviated titleProRISC


    • Clock Multiplier Unit
    • Jitter
    • Frequency Synthesis
    • CMOS
    • IR-67446
    • Oscillator
    • Phase Detector
    • Phase Locked Loop
    • EWI-14444
    • METIS-213464

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