A Low-jitter 2.5-to-10 GHz Clock Multiplier Unit in CMOS

R.C.H. van de Beek; C.S. Vaucher; D.M.W. Leenaerts; Eric A.M. Klumperink; Bram Nauta

A Low-jitter 2.5-to-10 GHz Clock Multiplier Unit in CMOS

R.C.H. van de Beek, C.S. Vaucher, D.M.W. Leenaerts, Eric A.M. Klumperink, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic

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Abstract

Abstract— This paper demonstrates a low-jitter clock multiplier unit [1] that generates a 10 GHz output clock from a 2.5 GHz reference clock. An integrated 10 GHz LCoscillator is locked to the input clock, using a simple and fast phase detector circuit. This phase detector overcomes the speed limitation of a conventional tri-state Phase Frequency Detector, by eliminating an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18¹m CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8 V supply.

Original language	Undefined
Title of host publication	the 14th ProRisc workshop on Circuits, Systems and Signal Processing (ProRisc 2003)
Place of Publication	Utrecht
Publisher	STW
Pages	173-176
Number of pages	4
ISBN (Print)	90-73461-39-1
Publication status	Published - Nov 2003
Event	14th ProRISC Workshop on Circuits, Systems and Signal Processing 2003 - Veldhoven, Netherlands Duration: 25 Nov 2003 → 27 Nov 2003 Conference number: 14

Publication series

Name
Publisher	STW Technology Foundation

Workshop

Workshop	14th ProRISC Workshop on Circuits, Systems and Signal Processing 2003
Abbreviated title	ProRISC
Country/Territory	Netherlands
City	Veldhoven
Period	25/11/03 → 27/11/03

Keywords

Clock Multiplier Unit
Jitter
Frequency Synthesis
CMOS
IR-67446
Oscillator
Phase Detector
Phase Locked Loop
EWI-14444
METIS-213464

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Cite this

@inproceedings{592ba0bcad674f7c9533acf3385dbdfa,

title = "A Low-jitter 2.5-to-10 GHz Clock Multiplier Unit in CMOS",

abstract = "Abstract— This paper demonstrates a low-jitter clock multiplier unit [1] that generates a 10 GHz output clock from a 2.5 GHz reference clock. An integrated 10 GHz LCoscillator is locked to the input clock, using a simple and fast phase detector circuit. This phase detector overcomes the speed limitation of a conventional tri-state Phase Frequency Detector, by eliminating an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18¹m CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8 V supply.",

keywords = "Clock Multiplier Unit, Jitter, Frequency Synthesis, CMOS, IR-67446, Oscillator, Phase Detector, Phase Locked Loop, EWI-14444, METIS-213464",

author = "{van de Beek}, R.C.H. and C.S. Vaucher and D.M.W. Leenaerts and Klumperink, {Eric A.M.} and Bram Nauta",

year = "2003",

month = nov,

language = "Undefined",

isbn = "90-73461-39-1",

publisher = "STW",

pages = "173--176",

booktitle = "the 14th ProRisc workshop on Circuits, Systems and Signal Processing (ProRisc 2003)",

note = "14th ProRISC Workshop on Circuits, Systems and Signal Processing 2003 ; Conference date: 25-11-2003 Through 27-11-2003",

}

TY - GEN

T1 - A Low-jitter 2.5-to-10 GHz Clock Multiplier Unit in CMOS

AU - van de Beek, R.C.H.

AU - Vaucher, C.S.

AU - Leenaerts, D.M.W.

AU - Klumperink, Eric A.M.

AU - Nauta, Bram

N1 - Conference code: 14

PY - 2003/11

Y1 - 2003/11

N2 - Abstract— This paper demonstrates a low-jitter clock multiplier unit [1] that generates a 10 GHz output clock from a 2.5 GHz reference clock. An integrated 10 GHz LCoscillator is locked to the input clock, using a simple and fast phase detector circuit. This phase detector overcomes the speed limitation of a conventional tri-state Phase Frequency Detector, by eliminating an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18¹m CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8 V supply.

AB - Abstract— This paper demonstrates a low-jitter clock multiplier unit [1] that generates a 10 GHz output clock from a 2.5 GHz reference clock. An integrated 10 GHz LCoscillator is locked to the input clock, using a simple and fast phase detector circuit. This phase detector overcomes the speed limitation of a conventional tri-state Phase Frequency Detector, by eliminating an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18¹m CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8 V supply.

KW - Clock Multiplier Unit

KW - Jitter

KW - Frequency Synthesis

KW - CMOS

KW - IR-67446

KW - Oscillator

KW - Phase Detector

KW - Phase Locked Loop

KW - EWI-14444

KW - METIS-213464

M3 - Conference contribution

SN - 90-73461-39-1

SP - 173

EP - 176

BT - the 14th ProRisc workshop on Circuits, Systems and Signal Processing (ProRisc 2003)

PB - STW

CY - Utrecht

T2 - 14th ProRISC Workshop on Circuits, Systems and Signal Processing 2003

Y2 - 25 November 2003 through 27 November 2003

ER -