A low noise, low residial offset chopped amplifier for mixed level applications

M.A.T. Sanduleanu; Adrianus Johannes Maria van Tuijl; R.F. Wassenaar; M.C. Lammers; Hans Wallinga

doi:10.1109/ICECS.1998.814893

A low noise, low residial offset chopped amplifier for mixed level applications

M.A.T. Sanduleanu
, Adrianus Johannes Maria van Tuijl
, R.F. Wassenaar
, M.C. Lammers
, Hans Wallinga

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

30 Citations (Scopus)

8 Downloads (Pure)

Abstract

This paper describes the principle and the design of a CMOS low noise, low residual offset, chopped amplifier with a class AB output stage for noise and offset reduction in mixed analog digital applications. The operation is based on chopping and dynamic element matching to reduce noise and offset, without excessive increase of the charge injection residual offset. The main goal is to achieve low residual offsets by chopping at high frequencies reducing at the same time the 1/f noise of the amplifier. Measurements on a 0.8 μm CMOS realization show reduction of 1/f noise and 18nV/√Hz residual thermal noise at low frequencies. The residual offset is lower than 100 μV up to 8 MHz chopping frequency. Driving a 32 Ω load the linearity is better than -80 dB and better than -88 dB for a 1 kΩ load at 1 kHz.

Original language	English
Title of host publication	5th IEEE International Conference on Electronics, Circuits and Systems, 1998 (Volume 2)
Place of Publication	Piscataway, NJ, USA
Publisher	IEEE
Pages	233-236
Number of pages	4
ISBN (Print)	0-7803-5008-1
DOIs	https://doi.org/10.1109/ICECS.1998.814893
Publication status	Published - 7 Sept 1998
Event	5th IEEE International Conference on Electronics, Circuits and Systems, ICECS '98 - Lisbon, Portugal Duration: 7 Sept 1998 → 10 Sept 1998 Conference number: 5

Publication series

Name
Publisher	IEEE

Conference

Conference	5th IEEE International Conference on Electronics, Circuits and Systems, ICECS '98
Abbreviated title	ICECS 1998
Country/Territory	Portugal
City	Lisbon
Period	7/09/98 → 10/09/98

Keywords

METIS-112982
IR-16097

Access to Document

10.1109/ICECS.1998.814893

Cite this

@inproceedings{654c425561ec42589dd561368f314a15,

title = "A low noise, low residial offset chopped amplifier for mixed level applications",

abstract = "This paper describes the principle and the design of a CMOS low noise, low residual offset, chopped amplifier with a class AB output stage for noise and offset reduction in mixed analog digital applications. The operation is based on chopping and dynamic element matching to reduce noise and offset, without excessive increase of the charge injection residual offset. The main goal is to achieve low residual offsets by chopping at high frequencies reducing at the same time the 1/f noise of the amplifier. Measurements on a 0.8 μm CMOS realization show reduction of 1/f noise and 18nV/√Hz residual thermal noise at low frequencies. The residual offset is lower than 100 μV up to 8 MHz chopping frequency. Driving a 32 Ω load the linearity is better than -80 dB and better than -88 dB for a 1 kΩ load at 1 kHz.",

keywords = "METIS-112982, IR-16097",

author = "M.A.T. Sanduleanu and \{van Tuijl\}, \{Adrianus Johannes Maria\} and R.F. Wassenaar and M.C. Lammers and Hans Wallinga",

year = "1998",

month = sep,

day = "7",

doi = "10.1109/ICECS.1998.814893",

language = "English",

isbn = "0-7803-5008-1",

publisher = "IEEE",

pages = "233--236",

booktitle = "5th IEEE International Conference on Electronics, Circuits and Systems, 1998 (Volume 2)",

address = "United States",

note = "5th IEEE International Conference on Electronics, Circuits and Systems, ICECS '98, ICECS 1998 ; Conference date: 07-09-1998 Through 10-09-1998",

}

Sanduleanu, MAT, van Tuijl, AJM, Wassenaar, RF, Lammers, MC & Wallinga, H 1998, A low noise, low residial offset chopped amplifier for mixed level applications. in 5th IEEE International Conference on Electronics, Circuits and Systems, 1998 (Volume 2). IEEE, Piscataway, NJ, USA, pp. 233-236, 5th IEEE International Conference on Electronics, Circuits and Systems, ICECS '98, Lisbon, Portugal, 7/09/98. https://doi.org/10.1109/ICECS.1998.814893

A low noise, low residial offset chopped amplifier for mixed level applications. / Sanduleanu, M.A.T.; van Tuijl, Adrianus Johannes Maria; Wassenaar, R.F. et al.
5th IEEE International Conference on Electronics, Circuits and Systems, 1998 (Volume 2). Piscataway, NJ, USA: IEEE, 1998. p. 233-236.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A low noise, low residial offset chopped amplifier for mixed level applications

AU - Sanduleanu, M.A.T.

AU - van Tuijl, Adrianus Johannes Maria

AU - Wassenaar, R.F.

AU - Lammers, M.C.

AU - Wallinga, Hans

N1 - Conference code: 5

PY - 1998/9/7

Y1 - 1998/9/7

N2 - This paper describes the principle and the design of a CMOS low noise, low residual offset, chopped amplifier with a class AB output stage for noise and offset reduction in mixed analog digital applications. The operation is based on chopping and dynamic element matching to reduce noise and offset, without excessive increase of the charge injection residual offset. The main goal is to achieve low residual offsets by chopping at high frequencies reducing at the same time the 1/f noise of the amplifier. Measurements on a 0.8 μm CMOS realization show reduction of 1/f noise and 18nV/√Hz residual thermal noise at low frequencies. The residual offset is lower than 100 μV up to 8 MHz chopping frequency. Driving a 32 Ω load the linearity is better than -80 dB and better than -88 dB for a 1 kΩ load at 1 kHz.

AB - This paper describes the principle and the design of a CMOS low noise, low residual offset, chopped amplifier with a class AB output stage for noise and offset reduction in mixed analog digital applications. The operation is based on chopping and dynamic element matching to reduce noise and offset, without excessive increase of the charge injection residual offset. The main goal is to achieve low residual offsets by chopping at high frequencies reducing at the same time the 1/f noise of the amplifier. Measurements on a 0.8 μm CMOS realization show reduction of 1/f noise and 18nV/√Hz residual thermal noise at low frequencies. The residual offset is lower than 100 μV up to 8 MHz chopping frequency. Driving a 32 Ω load the linearity is better than -80 dB and better than -88 dB for a 1 kΩ load at 1 kHz.

KW - METIS-112982

KW - IR-16097

U2 - 10.1109/ICECS.1998.814893

DO - 10.1109/ICECS.1998.814893

M3 - Conference contribution

SN - 0-7803-5008-1

SP - 233

EP - 236

BT - 5th IEEE International Conference on Electronics, Circuits and Systems, 1998 (Volume 2)

PB - IEEE

CY - Piscataway, NJ, USA

T2 - 5th IEEE International Conference on Electronics, Circuits and Systems, ICECS '98

Y2 - 7 September 1998 through 10 September 1998

ER -

A low noise, low residial offset chopped amplifier for mixed level applications

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