A Low Noise Sub-Sampling PLL in Which Divider Noise Is Eliminated and PD/CP Noise Is not multiplied by N2

X. Gao, Eric A.M. Klumperink, Mounhir Bohsali, Bram Nauta

    Research output: Contribution to journalArticleAcademicpeer-review

    121 Citations (Scopus)
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    Abstract

    Abstract—This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP)that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N2 in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. An added frequency locked loop guarantees correct frequency locking without degenerating jitter performance when in lock. The PLL is implemented in a standard 0.18- m CMOS process. It consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 X 0.45 mm蚠.With a frequency division ratio of 40, the in-band phase noise at 200 kHz offset is measured to be -126 dBc/Hz. The rms PLL output jitter integrated from 10 kHz to 40 MHz is 0.15 ps.
    Original languageEnglish
    Pages (from-to)3253-3263
    Number of pages11
    JournalIEEE journal of solid-state circuits
    Volume44
    Issue number12
    DOIs
    Publication statusPublished - 15 Dec 2009

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    Phase locked loops
    Pumps
    Sampling
    Detectors
    Jitter
    Variable frequency oscillators
    Phase noise
    Clocks

    Keywords

    • EWI-17308
    • IR-69683
    • METIS-264499

    Cite this

    @article{fa0c72a40b8340e18cf097b5f7e7bdf3,
    title = "A Low Noise Sub-Sampling PLL in Which Divider Noise Is Eliminated and PD/CP Noise Is not multiplied by N2",
    abstract = "Abstract—This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP)that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N2 in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. An added frequency locked loop guarantees correct frequency locking without degenerating jitter performance when in lock. The PLL is implemented in a standard 0.18- m CMOS process. It consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 X 0.45 mm蚠.With a frequency division ratio of 40, the in-band phase noise at 200 kHz offset is measured to be -126 dBc/Hz. The rms PLL output jitter integrated from 10 kHz to 40 MHz is 0.15 ps.",
    keywords = "EWI-17308, IR-69683, METIS-264499",
    author = "X. Gao and Klumperink, {Eric A.M.} and Mounhir Bohsali and Bram Nauta",
    year = "2009",
    month = "12",
    day = "15",
    doi = "10.1109/JSSC.2009.2032723",
    language = "English",
    volume = "44",
    pages = "3253--3263",
    journal = "IEEE journal of solid-state circuits",
    issn = "0018-9200",
    publisher = "IEEE",
    number = "12",

    }

    A Low Noise Sub-Sampling PLL in Which Divider Noise Is Eliminated and PD/CP Noise Is not multiplied by N2. / Gao, X.; Klumperink, Eric A.M.; Bohsali, Mounhir; Nauta, Bram.

    In: IEEE journal of solid-state circuits, Vol. 44, No. 12, 15.12.2009, p. 3253-3263.

    Research output: Contribution to journalArticleAcademicpeer-review

    TY - JOUR

    T1 - A Low Noise Sub-Sampling PLL in Which Divider Noise Is Eliminated and PD/CP Noise Is not multiplied by N2

    AU - Gao, X.

    AU - Klumperink, Eric A.M.

    AU - Bohsali, Mounhir

    AU - Nauta, Bram

    PY - 2009/12/15

    Y1 - 2009/12/15

    N2 - Abstract—This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP)that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N2 in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. An added frequency locked loop guarantees correct frequency locking without degenerating jitter performance when in lock. The PLL is implemented in a standard 0.18- m CMOS process. It consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 X 0.45 mm蚠.With a frequency division ratio of 40, the in-band phase noise at 200 kHz offset is measured to be -126 dBc/Hz. The rms PLL output jitter integrated from 10 kHz to 40 MHz is 0.15 ps.

    AB - Abstract—This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP)that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N2 in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. An added frequency locked loop guarantees correct frequency locking without degenerating jitter performance when in lock. The PLL is implemented in a standard 0.18- m CMOS process. It consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 X 0.45 mm蚠.With a frequency division ratio of 40, the in-band phase noise at 200 kHz offset is measured to be -126 dBc/Hz. The rms PLL output jitter integrated from 10 kHz to 40 MHz is 0.15 ps.

    KW - EWI-17308

    KW - IR-69683

    KW - METIS-264499

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    DO - 10.1109/JSSC.2009.2032723

    M3 - Article

    VL - 44

    SP - 3253

    EP - 3263

    JO - IEEE journal of solid-state circuits

    JF - IEEE journal of solid-state circuits

    SN - 0018-9200

    IS - 12

    ER -