A Low Speed BIST Framework for High Speed Circuit Testing

H. Speek, Hans G. Kerkhoff, M. Shashaani, M. Sachdev

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    4 Citations (Scopus)
    31 Downloads (Pure)

    Abstract

    Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a design-for-test methodology such that high performance devices can be tested on relatively low performance testers. In addition, a BIST framework is discussed based on this methodology. Various implementation aspects of this technique are also addressed
    Original languageUndefined
    Title of host publicationProceedings of IEEE VLSI Test Symposium
    Place of PublicationMontreal - Canada
    PublisherIEEE
    Pages349-355
    ISBN (Print)0769506135
    DOIs
    Publication statusPublished - 27 Jan 2000
    Event18th IEEE VLSI Test Symposium, VTS 2000 - Montreal, Canada
    Duration: 30 Apr 20004 May 2000
    Conference number: 18

    Publication series

    Name
    PublisherIEEE

    Other

    Other18th IEEE VLSI Test Symposium, VTS 2000
    Abbreviated titleVTS
    CountryCanada
    CityMontreal
    Period30/04/004/05/00

    Keywords

    • IR-16138
    • METIS-113023

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