A LUT-Based Approximate Adder

Andreas Becher; Jorge Echavarria; Daniel Ziener; Stefan Wildermann; Jürgen Teich

doi:10.1109/FCCM.2016.16

A LUT-Based Approximate Adder

Andreas Becher, Jorge Echavarria, Daniel Ziener, Stefan Wildermann, Jürgen Teich

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

17 Citations (Scopus)

1 Downloads (Pure)

Abstract

In this paper, we propose a novel approximate adder structure for LUT-based FPGA technology. Compared with a full featured accurate carry-ripple adder, the longest path is significantly shortened which enables the clocking with an increased clock frequency. By using the proposed adder structure, the throughput of an FPGA-based implementation can be significantly increased. On the other hand, the resulting average error can be reduced compared to similar approaches for ASIC implementations.

Original language	English
Title of host publication	24th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM)
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	27
Number of pages	1
ISBN (Electronic)	978-1-5090-2356-1
ISBN (Print)	978-1-5090-2357-8
DOIs	https://doi.org/10.1109/FCCM.2016.16
Publication status	Published - 16 Aug 2016
Externally published	Yes
Event	24th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016 - Washington, United States Duration: 1 May 2016 → 3 May 2016 Conference number: 24 http://www.fccm.org/2016/

Conference

Conference	24th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016
Abbreviated title	FCCM
Country/Territory	United States
City	Washington
Period	1/05/16 → 3/05/16
Internet address	http://www.fccm.org/2016/

Keywords

Adders
Approximate Computing
FPGAs
Low Power
LUTs
n/a OA procedure

Access to Document

10.1109/FCCM.2016.16

Cite this

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title = "A LUT-Based Approximate Adder",

abstract = "In this paper, we propose a novel approximate adder structure for LUT-based FPGA technology. Compared with a full featured accurate carry-ripple adder, the longest path is significantly shortened which enables the clocking with an increased clock frequency. By using the proposed adder structure, the throughput of an FPGA-based implementation can be significantly increased. On the other hand, the resulting average error can be reduced compared to similar approaches for ASIC implementations.",

keywords = "Adders, Approximate Computing, FPGAs, Low Power, LUTs, n/a OA procedure",

author = "Andreas Becher and Jorge Echavarria and Daniel Ziener and Stefan Wildermann and J{\"u}rgen Teich",

year = "2016",

month = aug,

day = "16",

doi = "10.1109/FCCM.2016.16",

language = "English",

isbn = "978-1-5090-2357-8",

pages = "27",

booktitle = "24th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM)",

publisher = "IEEE",

address = "United States",

note = "24th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016, FCCM ; Conference date: 01-05-2016 Through 03-05-2016",

url = "http://www.fccm.org/2016/",

}

Becher, A, Echavarria, J, Ziener, D, Wildermann, S & Teich, J 2016, A LUT-Based Approximate Adder. in 24th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM)., 7544739, IEEE, Piscataway, NJ, pp. 27, 24th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016, Washington, District of Columbia, United States, 1/05/16. https://doi.org/10.1109/FCCM.2016.16

TY - GEN

T1 - A LUT-Based Approximate Adder

AU - Becher, Andreas

AU - Echavarria, Jorge

AU - Ziener, Daniel

AU - Wildermann, Stefan

AU - Teich, Jürgen

N1 - Conference code: 24

PY - 2016/8/16

Y1 - 2016/8/16

N2 - In this paper, we propose a novel approximate adder structure for LUT-based FPGA technology. Compared with a full featured accurate carry-ripple adder, the longest path is significantly shortened which enables the clocking with an increased clock frequency. By using the proposed adder structure, the throughput of an FPGA-based implementation can be significantly increased. On the other hand, the resulting average error can be reduced compared to similar approaches for ASIC implementations.

AB - In this paper, we propose a novel approximate adder structure for LUT-based FPGA technology. Compared with a full featured accurate carry-ripple adder, the longest path is significantly shortened which enables the clocking with an increased clock frequency. By using the proposed adder structure, the throughput of an FPGA-based implementation can be significantly increased. On the other hand, the resulting average error can be reduced compared to similar approaches for ASIC implementations.

KW - Adders

KW - Approximate Computing

KW - FPGAs

KW - Low Power

KW - LUTs

KW - n/a OA procedure

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U2 - 10.1109/FCCM.2016.16

DO - 10.1109/FCCM.2016.16

M3 - Conference contribution

AN - SCOPUS:84987629378

SN - 978-1-5090-2357-8

SP - 27

BT - 24th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM)

PB - IEEE

CY - Piscataway, NJ

T2 - 24th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016

Y2 - 1 May 2016 through 3 May 2016

ER -

A LUT-Based Approximate Adder

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