A LUT-Based Approximate Adder

Andreas Becher, Jorge Echavarria, Daniel Ziener, Stefan Wildermann, Jürgen Teich

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    10 Citations (Scopus)
    1 Downloads (Pure)

    Abstract

    In this paper, we propose a novel approximate adder structure for LUT-based FPGA technology. Compared with a full featured accurate carry-ripple adder, the longest path is significantly shortened which enables the clocking with an increased clock frequency. By using the proposed adder structure, the throughput of an FPGA-based implementation can be significantly increased. On the other hand, the resulting average error can be reduced compared to similar approaches for ASIC implementations.

    Original languageEnglish
    Title of host publication24th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM)
    Place of PublicationPiscataway, NJ
    PublisherIEEE
    Pages27
    Number of pages1
    ISBN (Electronic)978-1-5090-2356-1
    ISBN (Print)978-1-5090-2357-8
    DOIs
    Publication statusPublished - 16 Aug 2016
    Event24th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016 - Washington, United States
    Duration: 1 May 20163 May 2016
    Conference number: 24
    http://www.fccm.org/2016/

    Conference

    Conference24th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016
    Abbreviated titleFCCM
    CountryUnited States
    CityWashington
    Period1/05/163/05/16
    Internet address

    Keywords

    • Adders
    • Approximate Computing
    • FPGAs
    • Low Power
    • LUTs

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  • Cite this

    Becher, A., Echavarria, J., Ziener, D., Wildermann, S., & Teich, J. (2016). A LUT-Based Approximate Adder. In 24th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) (pp. 27). [7544739] Piscataway, NJ: IEEE. https://doi.org/10.1109/FCCM.2016.16