A mathematical approach towards hardware design

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    Abstract

    Today the hardware for embedded systems is often specified in VHDL. However, VHDL describes the system at a rather low level, which is cumbersome and may lead to design faults in large real life applications. There is a need of higher level abstraction mechanisms. In the embedded systems group of the University of Twente we are working on systematic and transformational methods to design hardware architectures, both multi core and single core. The main line in this approach is to start with a straightforward (often mathematical) specification of the problem. The next step is to find some adequate transformations on this specification, in particular to find specific optimizations, to be able to distribute the application over different cores. The result of these transformations is then translated into the functional programming language Haskell since Haskell is close to mathematics and such a translation often is straightforward. Besides, the Haskell code is executable, so one immediately has a simulation of the intended system. Next, the resulting Haskell specification is given to a compiler, called CëaSH (for CAES LAnguage for Synchronous Hardware) which translates the specification into VHDL. The resulting VHDL is synthesizable, so from there on standard VHDL-tooling can be used for synthesis. In this work we primarily focus on streaming applications: i.e. applications that can be modeled as data-flow graphs. At the moment the CëaSH system is ready in prototype form and in the presentation we will give several examples of how it can be used. In these examples it will be shown that the specification code is clear and concise. Furthermore, it is possible to use powerful abstraction mechanisms, such as polymorphism, higher order functions, pattern matching, lambda abstraction, partial application. These features allow a designer to describe circuits in a more natural and concise way than possible with the language elements found in the traditional hardware description languages. In addition we will give some examples of transformations that are possible in a mathematical specification, and which do not suffer from the problems encountered in, e.g., automatic parallelization of nested for-loops in C-programs.
    Original languageUndefined
    Title of host publicationDagstuhl Seminar on Dynamically Reconfigurable Architectures
    EditorsP.M. Athanas, J. Becker, J. Teich, I. Verbauwhede
    Place of PublicationDagstuhl, Germany
    PublisherInternationales Begegnungs- und Forschungszentrum für Informatik
    Pages11
    Number of pages11
    DOIs
    Publication statusPublished - 14 Dec 2010
    EventDagstuhl Seminar on Dynamically Reconfigurable Architectures - Dagstuhl, Germany
    Duration: 11 Jul 201016 Jul 2010

    Publication series

    NameDagstuhl Seminar Proceedings
    PublisherInternationales Begegnungs- und Forschungszentrum für Informatik (IBFI)
    Volume10281
    ISSN (Print)1862-4405

    Conference

    ConferenceDagstuhl Seminar on Dynamically Reconfigurable Architectures
    Period11/07/1016/07/10
    Other11-16 July 2010

    Keywords

    • IR-75334
    • METIS-275806
    • Hardware design
    • EC Grant Agreement nr.: FP7/248465
    • Streaming Applications
    • EWI-19169
    • mathematical specification

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