### Abstract

Language | Undefined |
---|---|

Title of host publication | Dagstuhl Seminar on Dynamically Reconfigurable Architectures |

Editors | P.M. Athanas, J. Becker, J. Teich, I. Verbauwhede |

Place of Publication | Dagstuhl, Germany |

Publisher | Internationales Begegnungs- und Forschungszentrum für Informatik |

Pages | 11 |

Number of pages | 11 |

DOIs | |

Publication status | Published - 14 Dec 2010 |

### Publication series

Name | Dagstuhl Seminar Proceedings |
---|---|

Publisher | Internationales Begegnungs- und Forschungszentrum für Informatik (IBFI) |

Volume | 10281 |

ISSN (Print) | 1862-4405 |

### Keywords

- IR-75334
- METIS-275806
- Hardware design
- EC Grant Agreement nr.: FP7/248465
- Streaming Applications
- EWI-19169
- mathematical specification

### Cite this

*Dagstuhl Seminar on Dynamically Reconfigurable Architectures*(pp. 11). (Dagstuhl Seminar Proceedings; Vol. 10281). Dagstuhl, Germany: Internationales Begegnungs- und Forschungszentrum für Informatik. https://doi.org/10.4230/OASIcs.WCET.2010.136

}

*Dagstuhl Seminar on Dynamically Reconfigurable Architectures.*Dagstuhl Seminar Proceedings, vol. 10281, Internationales Begegnungs- und Forschungszentrum für Informatik, Dagstuhl, Germany, pp. 11. https://doi.org/10.4230/OASIcs.WCET.2010.136

**A mathematical approach towards hardware design.** / Smit, Gerardus Johannes Maria; Kuper, Jan; Baaij, C.P.R.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A mathematical approach towards hardware design

AU - Smit, Gerardus Johannes Maria

AU - Kuper, Jan

AU - Baaij, C.P.R.

N1 - eemcs-eprint-19169

PY - 2010/12/14

Y1 - 2010/12/14

N2 - Today the hardware for embedded systems is often specified in VHDL. However, VHDL describes the system at a rather low level, which is cumbersome and may lead to design faults in large real life applications. There is a need of higher level abstraction mechanisms. In the embedded systems group of the University of Twente we are working on systematic and transformational methods to design hardware architectures, both multi core and single core. The main line in this approach is to start with a straightforward (often mathematical) specification of the problem. The next step is to find some adequate transformations on this specification, in particular to find specific optimizations, to be able to distribute the application over different cores. The result of these transformations is then translated into the functional programming language Haskell since Haskell is close to mathematics and such a translation often is straightforward. Besides, the Haskell code is executable, so one immediately has a simulation of the intended system. Next, the resulting Haskell specification is given to a compiler, called CëaSH (for CAES LAnguage for Synchronous Hardware) which translates the specification into VHDL. The resulting VHDL is synthesizable, so from there on standard VHDL-tooling can be used for synthesis. In this work we primarily focus on streaming applications: i.e. applications that can be modeled as data-flow graphs. At the moment the CëaSH system is ready in prototype form and in the presentation we will give several examples of how it can be used. In these examples it will be shown that the specification code is clear and concise. Furthermore, it is possible to use powerful abstraction mechanisms, such as polymorphism, higher order functions, pattern matching, lambda abstraction, partial application. These features allow a designer to describe circuits in a more natural and concise way than possible with the language elements found in the traditional hardware description languages. In addition we will give some examples of transformations that are possible in a mathematical specification, and which do not suffer from the problems encountered in, e.g., automatic parallelization of nested for-loops in C-programs.

AB - Today the hardware for embedded systems is often specified in VHDL. However, VHDL describes the system at a rather low level, which is cumbersome and may lead to design faults in large real life applications. There is a need of higher level abstraction mechanisms. In the embedded systems group of the University of Twente we are working on systematic and transformational methods to design hardware architectures, both multi core and single core. The main line in this approach is to start with a straightforward (often mathematical) specification of the problem. The next step is to find some adequate transformations on this specification, in particular to find specific optimizations, to be able to distribute the application over different cores. The result of these transformations is then translated into the functional programming language Haskell since Haskell is close to mathematics and such a translation often is straightforward. Besides, the Haskell code is executable, so one immediately has a simulation of the intended system. Next, the resulting Haskell specification is given to a compiler, called CëaSH (for CAES LAnguage for Synchronous Hardware) which translates the specification into VHDL. The resulting VHDL is synthesizable, so from there on standard VHDL-tooling can be used for synthesis. In this work we primarily focus on streaming applications: i.e. applications that can be modeled as data-flow graphs. At the moment the CëaSH system is ready in prototype form and in the presentation we will give several examples of how it can be used. In these examples it will be shown that the specification code is clear and concise. Furthermore, it is possible to use powerful abstraction mechanisms, such as polymorphism, higher order functions, pattern matching, lambda abstraction, partial application. These features allow a designer to describe circuits in a more natural and concise way than possible with the language elements found in the traditional hardware description languages. In addition we will give some examples of transformations that are possible in a mathematical specification, and which do not suffer from the problems encountered in, e.g., automatic parallelization of nested for-loops in C-programs.

KW - IR-75334

KW - METIS-275806

KW - Hardware design

KW - EC Grant Agreement nr.: FP7/248465

KW - Streaming Applications

KW - EWI-19169

KW - mathematical specification

U2 - 10.4230/OASIcs.WCET.2010.136

DO - 10.4230/OASIcs.WCET.2010.136

M3 - Conference contribution

T3 - Dagstuhl Seminar Proceedings

SP - 11

BT - Dagstuhl Seminar on Dynamically Reconfigurable Architectures

A2 - Athanas, P.M.

A2 - Becker, J.

A2 - Teich, J.

A2 - Verbauwhede, I.

PB - Internationales Begegnungs- und Forschungszentrum für Informatik

CY - Dagstuhl, Germany

ER -