A multi-ASIC real-time implementation of the two dimensional affine transform with a bilinear interpolation scheme

Mark J. Bentum, Martin M. Samsom, Martin M. Samsom, Cornelis H. Slump

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    2 Citations (Scopus)
    134 Downloads (Pure)

    Abstract

    Some image processing applications (e.g. computer graphics and robot vision) require the rotation, scaling and translation of digitized images in real-time (25–30 images per second). Today's standard image processors can not meet this timing constraint so other solutions have to be considered. This paper describes a multi-ASIC solution which is capable of doing the image processing tasks in real-time. The first ASIC is a so-called affine transformer which calculates a one-dimensional coordinate every 25 ns. The second ASIC is a bilinear interpolator which calculates an interpolated value from four known surrounding values, again every 25 ns. This ASIC is designed in a modular setup which results in a flexible accuracy of the interpolation. If more accurate interpolation is required, another ASIC (containing an interpolation stage) is used. In this way for each application a proper accuracy is implemented, reaching optimal silicon area utilization and desired accuracy of interpolation. Using two affine transformers (for obtaining a two dimensional coordinate pair) and an interpolator, one can build a system which can translate, rotate and scale an image of size 1024 * 1024 in real-time (25–30 images per second). In this paper the system as well as the design of the ASICs are presented.
    Original languageEnglish
    Pages (from-to)261-273
    JournalJournal of VLSI signal processing
    Volume10
    Issue number3
    DOIs
    Publication statusPublished - 1995

    Keywords

    • Input image
    • Print circuit board
    • Output image
    • Bilinear interpolation
    • Coordinate pair

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