@inproceedings{cc3df71f205949bdb285cc475e1df7cf,
title = "A new hierachical approach to test-pattern generation",
abstract = "The authors present a new and fully hierarchical approach to automatic test-pattern generation, for digital MOS VLSI circuits. The description of a VLSI circuit consists of several hierarchical levels of interconnected modules. Each module consists of one or more sub-modules are functionally described by ordered binary decision diagrams (OBDD). The OBDDs of its sub-modules, starting from the lowest-level modules. Test-patterns are generated for each module using previously generated test-patterns for its sub-modules, starting at the switch-level. Accurate fault models, like the line stuck-at and switch stuck-on/open models, are used to model physical defects. At higher levels, faults are modeled by the test-patterns covering the fault. Results on large combinatorial circuits confirm the feasibility of the new test-pattern generation approach, and its superiority over conventional non-hierarchical methods",
keywords = "METIS-112962, IR-16078",
author = "E.C. Weening and Weening, {Edward C.} and Kerkhoff, {Hans G.}",
year = "1991",
month = sep,
day = "1",
doi = "10.1109/ASIC.1991.242855",
language = "Undefined",
publisher = "IEEE",
pages = "6.1.1--6.1.4",
booktitle = "Proceedings IEEE Int. ASIC Conference and Exhibit",
address = "United States",
note = "Fourth Annual IEEE International ASIC Conference and Exhibit ; Conference date: 23-09-1991 Through 27-09-1991",
}