A new hierachical approach to test-pattern generation

E.C. Weening, Edward C. Weening, Hans G. Kerkhoff

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    Abstract

    The authors present a new and fully hierarchical approach to automatic test-pattern generation, for digital MOS VLSI circuits. The description of a VLSI circuit consists of several hierarchical levels of interconnected modules. Each module consists of one or more sub-modules are functionally described by ordered binary decision diagrams (OBDD). The OBDDs of its sub-modules, starting from the lowest-level modules. Test-patterns are generated for each module using previously generated test-patterns for its sub-modules, starting at the switch-level. Accurate fault models, like the line stuck-at and switch stuck-on/open models, are used to model physical defects. At higher levels, faults are modeled by the test-patterns covering the fault. Results on large combinatorial circuits confirm the feasibility of the new test-pattern generation approach, and its superiority over conventional non-hierarchical methods
    Original languageUndefined
    Title of host publicationProceedings IEEE Int. ASIC Conference and Exhibit
    Place of PublicationRochester
    PublisherIEEE
    Pages6.1.1-6.1.4
    Number of pages0
    DOIs
    Publication statusPublished - 1 Sep 1991
    EventFourth Annual IEEE International ASIC Conference and Exhibit - Rochester, NY
    Duration: 23 Sep 199127 Sep 1991

    Publication series

    Name
    PublisherIEEE

    Conference

    ConferenceFourth Annual IEEE International ASIC Conference and Exhibit
    Period23/09/9127/09/91
    Other23-27 Sept. 1991

    Keywords

    • METIS-112962
    • IR-16078

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