A new hierachical approach to test-pattern generation

E.C. Weening; Edward C. Weening; Hans G. Kerkhoff

doi:10.1109/ASIC.1991.242855

A new hierachical approach to test-pattern generation

E.C. Weening, Edward C. Weening, Hans G. Kerkhoff

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

The authors present a new and fully hierarchical approach to automatic test-pattern generation, for digital MOS VLSI circuits. The description of a VLSI circuit consists of several hierarchical levels of interconnected modules. Each module consists of one or more sub-modules are functionally described by ordered binary decision diagrams (OBDD). The OBDDs of its sub-modules, starting from the lowest-level modules. Test-patterns are generated for each module using previously generated test-patterns for its sub-modules, starting at the switch-level. Accurate fault models, like the line stuck-at and switch stuck-on/open models, are used to model physical defects. At higher levels, faults are modeled by the test-patterns covering the fault. Results on large combinatorial circuits confirm the feasibility of the new test-pattern generation approach, and its superiority over conventional non-hierarchical methods

Original language	Undefined
Title of host publication	Proceedings IEEE Int. ASIC Conference and Exhibit
Place of Publication	Rochester
Publisher	IEEE
Pages	6.1.1-6.1.4
Number of pages	0
DOIs	https://doi.org/10.1109/ASIC.1991.242855
Publication status	Published - 1 Sept 1991
Event	Fourth Annual IEEE International ASIC Conference and Exhibit - Rochester, NY Duration: 23 Sept 1991 → 27 Sept 1991

Publication series

Name
Publisher	IEEE

Conference

Conference	Fourth Annual IEEE International ASIC Conference and Exhibit
Period	23/09/91 → 27/09/91
Other	23-27 Sept. 1991

Keywords

METIS-112962
IR-16078

Access to Document

10.1109/ASIC.1991.242855

00242855

Cite this

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title = "A new hierachical approach to test-pattern generation",

abstract = "The authors present a new and fully hierarchical approach to automatic test-pattern generation, for digital MOS VLSI circuits. The description of a VLSI circuit consists of several hierarchical levels of interconnected modules. Each module consists of one or more sub-modules are functionally described by ordered binary decision diagrams (OBDD). The OBDDs of its sub-modules, starting from the lowest-level modules. Test-patterns are generated for each module using previously generated test-patterns for its sub-modules, starting at the switch-level. Accurate fault models, like the line stuck-at and switch stuck-on/open models, are used to model physical defects. At higher levels, faults are modeled by the test-patterns covering the fault. Results on large combinatorial circuits confirm the feasibility of the new test-pattern generation approach, and its superiority over conventional non-hierarchical methods",

keywords = "METIS-112962, IR-16078",

author = "E.C. Weening and Weening, {Edward C.} and Kerkhoff, {Hans G.}",

year = "1991",

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doi = "10.1109/ASIC.1991.242855",

language = "Undefined",

publisher = "IEEE",

pages = "6.1.1--6.1.4",

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note = "Fourth Annual IEEE International ASIC Conference and Exhibit ; Conference date: 23-09-1991 Through 27-09-1991",

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AU - Kerkhoff, Hans G.

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N2 - The authors present a new and fully hierarchical approach to automatic test-pattern generation, for digital MOS VLSI circuits. The description of a VLSI circuit consists of several hierarchical levels of interconnected modules. Each module consists of one or more sub-modules are functionally described by ordered binary decision diagrams (OBDD). The OBDDs of its sub-modules, starting from the lowest-level modules. Test-patterns are generated for each module using previously generated test-patterns for its sub-modules, starting at the switch-level. Accurate fault models, like the line stuck-at and switch stuck-on/open models, are used to model physical defects. At higher levels, faults are modeled by the test-patterns covering the fault. Results on large combinatorial circuits confirm the feasibility of the new test-pattern generation approach, and its superiority over conventional non-hierarchical methods

AB - The authors present a new and fully hierarchical approach to automatic test-pattern generation, for digital MOS VLSI circuits. The description of a VLSI circuit consists of several hierarchical levels of interconnected modules. Each module consists of one or more sub-modules are functionally described by ordered binary decision diagrams (OBDD). The OBDDs of its sub-modules, starting from the lowest-level modules. Test-patterns are generated for each module using previously generated test-patterns for its sub-modules, starting at the switch-level. Accurate fault models, like the line stuck-at and switch stuck-on/open models, are used to model physical defects. At higher levels, faults are modeled by the test-patterns covering the fault. Results on large combinatorial circuits confirm the feasibility of the new test-pattern generation approach, and its superiority over conventional non-hierarchical methods

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KW - IR-16078

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DO - 10.1109/ASIC.1991.242855

M3 - Conference contribution

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