A New Test Generation Approach for Embedded Analogue Cores in SoC

M. Stancic; L. Fang; M.H.H. Weusthof; R.M.W. Tijink; H.G. Kerkhoff

doi:10.1109/TEST.2002.1041840

A New Test Generation Approach for Embedded Analogue Cores in SoC

M. Stancic, L. Fang, M.H.H. Weusthof, R.M.W. Tijink, H.G. Kerkhoff

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

3 Citations (Scopus)

138 Downloads (Pure)

Abstract

This paper proposes a new test-generation approach for embedded analogue cores in SoC. The key features of this approach are the developed testability-analysis based multifrequency test pattern generation method, the novel PID feedback-based test signal backtrace procedure and the fast tolerance-box propagation algorithm. Moreover, possible DFT solutions are discussed. Finally, this approach has been validated by experiments conducted on a real hardware implementation.

Original language	English
Title of host publication	Proceedings International Test Conference 2002
Subtitle of host publication	October 7-10, 2002, Baltimore Convention Center, MD, USA.
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	861-869
Number of pages	9
ISBN (Print)	0-7803-7542-4
DOIs	https://doi.org/10.1109/TEST.2002.1041840
Publication status	Published - 6 Oct 2002
Event	International Test Conference, ITC 2002 - Baltimore, United States Duration: 7 Oct 2002 → 10 Oct 2002

Conference

Conference	International Test Conference, ITC 2002
Abbreviated title	ITC
Country/Territory	United States
City	Baltimore
Period	7/10/02 → 10/10/02

Keywords

2023 OA procedure

Access to Document

10.1109/TEST.2002.1041840

ArticleFinal published version, 616 KBLicence: Taverne

Cite this

@inproceedings{8827013ced084c16b7d00a9aa5d3d1fb,

title = "A New Test Generation Approach for Embedded Analogue Cores in SoC",

abstract = "This paper proposes a new test-generation approach for embedded analogue cores in SoC. The key features of this approach are the developed testability-analysis based multifrequency test pattern generation method, the novel PID feedback-based test signal backtrace procedure and the fast tolerance-box propagation algorithm. Moreover, possible DFT solutions are discussed. Finally, this approach has been validated by experiments conducted on a real hardware implementation.",

keywords = "2023 OA procedure",

author = "M. Stancic and L. Fang and M.H.H. Weusthof and R.M.W. Tijink and H.G. Kerkhoff",

year = "2002",

month = oct,

day = "6",

doi = "10.1109/TEST.2002.1041840",

language = "English",

isbn = "0-7803-7542-4",

pages = "861--869",

booktitle = "Proceedings International Test Conference 2002",

publisher = "IEEE",

address = "United States",

note = "International Test Conference, ITC 2002, ITC ; Conference date: 07-10-2002 Through 10-10-2002",

}

Stancic, M, Fang, L, Weusthof, MHH, Tijink, RMW & Kerkhoff, HG 2002, A New Test Generation Approach for Embedded Analogue Cores in SoC. in Proceedings International Test Conference 2002: October 7-10, 2002, Baltimore Convention Center, MD, USA.. IEEE, Piscataway, NJ, pp. 861-869, International Test Conference, ITC 2002, Baltimore, Maryland, United States, 7/10/02. https://doi.org/10.1109/TEST.2002.1041840

A New Test Generation Approach for Embedded Analogue Cores in SoC. / Stancic, M.; Fang, L.; Weusthof, M.H.H. et al.
Proceedings International Test Conference 2002: October 7-10, 2002, Baltimore Convention Center, MD, USA.. Piscataway, NJ: IEEE, 2002. p. 861-869.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A New Test Generation Approach for Embedded Analogue Cores in SoC

AU - Stancic, M.

AU - Fang, L.

AU - Weusthof, M.H.H.

AU - Tijink, R.M.W.

AU - Kerkhoff, H.G.

PY - 2002/10/6

Y1 - 2002/10/6

N2 - This paper proposes a new test-generation approach for embedded analogue cores in SoC. The key features of this approach are the developed testability-analysis based multifrequency test pattern generation method, the novel PID feedback-based test signal backtrace procedure and the fast tolerance-box propagation algorithm. Moreover, possible DFT solutions are discussed. Finally, this approach has been validated by experiments conducted on a real hardware implementation.

AB - This paper proposes a new test-generation approach for embedded analogue cores in SoC. The key features of this approach are the developed testability-analysis based multifrequency test pattern generation method, the novel PID feedback-based test signal backtrace procedure and the fast tolerance-box propagation algorithm. Moreover, possible DFT solutions are discussed. Finally, this approach has been validated by experiments conducted on a real hardware implementation.

KW - 2023 OA procedure

U2 - 10.1109/TEST.2002.1041840

DO - 10.1109/TEST.2002.1041840

M3 - Conference contribution

SN - 0-7803-7542-4

SP - 861

EP - 869

BT - Proceedings International Test Conference 2002

PB - IEEE

CY - Piscataway, NJ

T2 - International Test Conference, ITC 2002

Y2 - 7 October 2002 through 10 October 2002

ER -

A New Test Generation Approach for Embedded Analogue Cores in SoC

Abstract

Conference

Keywords

Access to Document

Fingerprint

Cite this