A New Test Generation Approach for Embedded Analogue Cores in SoC

M. Stancic, L. Fang, Marcel H.H. Weusthof, R.M.W. Tijink, Hans G. Kerkhoff

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    2 Citations (Scopus)
    53 Downloads (Pure)

    Abstract

    This paper proposes a new test-generation approach for embedded analogue cores in SoC. The key features of this approach are the developed testability-analysis based multifrequency test pattern generation method, the novel PID feedback-based test signal backtrace procedure and the fast tolerance-box propagation algorithm. Moreover, possible DFT solutions are discussed. Finally, this approach has been validated by experiments conducted on a real hardware implementation.
    Original languageUndefined
    Title of host publicationProceedings International Test Conference
    Place of PublicationBaltimore, USA
    PublisherInternational Test Conference
    Pages861-869
    Number of pages9
    ISBN (Print)0-7803-7542-4
    DOIs
    Publication statusPublished - 6 Oct 2002
    EventInternational Test Conference, 2002 - Baltimore, USA
    Duration: 7 Oct 200210 Oct 2002

    Publication series

    Name
    PublisherInternational Test Conference

    Conference

    ConferenceInternational Test Conference, 2002
    Period7/10/0210/10/02
    Other7-10 Oct. 2002

    Keywords

    • IR-43873
    • METIS-207630

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