A New Test Generation Approach for Embedded Analogue Cores in SoC

M. Stancic; L. Fang; Marcel H.H. Weusthof; R.M.W. Tijink; Hans G. Kerkhoff

doi:10.1109/TEST.2002.1041840

A New Test Generation Approach for Embedded Analogue Cores in SoC

M. Stancic, L. Fang, Marcel H.H. Weusthof, R.M.W. Tijink, Hans G. Kerkhoff

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

3 Citations (Scopus)

109 Downloads (Pure)

Abstract

This paper proposes a new test-generation approach for embedded analogue cores in SoC. The key features of this approach are the developed testability-analysis based multifrequency test pattern generation method, the novel PID feedback-based test signal backtrace procedure and the fast tolerance-box propagation algorithm. Moreover, possible DFT solutions are discussed. Finally, this approach has been validated by experiments conducted on a real hardware implementation.

Original language	Undefined
Title of host publication	Proceedings International Test Conference
Place of Publication	Baltimore, USA
Publisher	International Test Conference
Pages	861-869
Number of pages	9
ISBN (Print)	0-7803-7542-4
DOIs	https://doi.org/10.1109/TEST.2002.1041840
Publication status	Published - 6 Oct 2002
Event	International Test Conference, 2002 - Baltimore, USA Duration: 7 Oct 2002 → 10 Oct 2002

Publication series

Name
Publisher	International Test Conference

Conference

Conference	International Test Conference, 2002
Period	7/10/02 → 10/10/02
Other	7-10 Oct. 2002

Keywords

IR-43873
METIS-207630

Access to Document

10.1109/TEST.2002.1041840

01041840

Cite this

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title = "A New Test Generation Approach for Embedded Analogue Cores in SoC",

abstract = "This paper proposes a new test-generation approach for embedded analogue cores in SoC. The key features of this approach are the developed testability-analysis based multifrequency test pattern generation method, the novel PID feedback-based test signal backtrace procedure and the fast tolerance-box propagation algorithm. Moreover, possible DFT solutions are discussed. Finally, this approach has been validated by experiments conducted on a real hardware implementation.",

keywords = "IR-43873, METIS-207630",

author = "M. Stancic and L. Fang and Weusthof, {Marcel H.H.} and R.M.W. Tijink and Kerkhoff, {Hans G.}",

year = "2002",

month = oct,

day = "6",

doi = "10.1109/TEST.2002.1041840",

language = "Undefined",

isbn = "0-7803-7542-4",

publisher = "International Test Conference",

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T1 - A New Test Generation Approach for Embedded Analogue Cores in SoC

AU - Stancic, M.

AU - Fang, L.

AU - Weusthof, Marcel H.H.

AU - Tijink, R.M.W.

AU - Kerkhoff, Hans G.

PY - 2002/10/6

Y1 - 2002/10/6

N2 - This paper proposes a new test-generation approach for embedded analogue cores in SoC. The key features of this approach are the developed testability-analysis based multifrequency test pattern generation method, the novel PID feedback-based test signal backtrace procedure and the fast tolerance-box propagation algorithm. Moreover, possible DFT solutions are discussed. Finally, this approach has been validated by experiments conducted on a real hardware implementation.

AB - This paper proposes a new test-generation approach for embedded analogue cores in SoC. The key features of this approach are the developed testability-analysis based multifrequency test pattern generation method, the novel PID feedback-based test signal backtrace procedure and the fast tolerance-box propagation algorithm. Moreover, possible DFT solutions are discussed. Finally, this approach has been validated by experiments conducted on a real hardware implementation.

KW - IR-43873

KW - METIS-207630

U2 - 10.1109/TEST.2002.1041840

DO - 10.1109/TEST.2002.1041840

M3 - Conference contribution

SN - 0-7803-7542-4

SP - 861

EP - 869

BT - Proceedings International Test Conference

PB - International Test Conference

CY - Baltimore, USA

Y2 - 7 October 2002 through 10 October 2002

ER -