A New Test Generation Approach for Embedded Analogue Cores in SoC

M. Stancic, L. Fang, Marcel H.H. Weusthof, R.M.W. Tijink, Hans G. Kerkhoff

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    This paper proposes a new test-generation approach for embedded analogue cores in SoC. The key features of this approach are the developed testability-analysis based multifrequency test pattern generation method, the novel PID feedback-based test signal backtrace procedure and the fast tolerance-box propagation algorithm. Moreover, possible DFT solutions are discussed. Finally, this approach has been validated by experiments conducted on a real hardware implementation.
    Original languageUndefined
    Title of host publicationProceedings International Test Conference
    Place of PublicationBaltimore, USA
    PublisherInternational Test Conference
    Number of pages9
    ISBN (Print)0-7803-7542-4
    Publication statusPublished - 6 Oct 2002

    Publication series

    PublisherInternational Test Conference


    • IR-43873
    • METIS-207630

    Cite this

    Stancic, M., Fang, L., Weusthof, M. H. H., Tijink, R. M. W., & Kerkhoff, H. G. (2002). A New Test Generation Approach for Embedded Analogue Cores in SoC. In Proceedings International Test Conference (pp. 861-869). Baltimore, USA: International Test Conference. https://doi.org/10.1109/TEST.2002.1041840