A “No Gain” Direct-Conversion IQ RF-to-Bits Receiver Without Active Linear Amplification

This work describes a direct-conversion IQ receiver (RX) that does not utilize any active linear (power) amplification, covering its design considerations, prototype implementation, and measurement verification. Only RLC components, MOS transistor (MOST) switches, and comparators are used, leading to several unique design challenges. Key among these are the fact that each block in the signal chain contributes to overall loss, together setting the RF input impedance and thereby RX input matching, plus the limited frequency selectivity of the available passive filters. By considering a fundamental minimum power consumption limit of analog-to-digital converters (ADCs) given by Vittoz, we show that applying impedance up-transformation in the RF front end (RFE) lowers the (minimal) power consumption of the back-end quantization ADC. In our proposed RX, this is implemented by a resonant monolithic transformer followed by a capacitive-stacking N-path filter/mixer (CSNPFM). The resulting RFE architecture simultaneously implements blocker rejection, frequency translation to baseband (BB), and a ~40x power consumption reduction in the back-end ADC. The poor frequency selectivity of passive integrated filters renders the implementation of anti-alias filter (AAF) challenging. To avoid their necessity, a highly oversampled delta-sigma modulator back end synchronously digitizes the CSNPFM’s output samples. A prototype RX, implemented in a 22 nm fully-depleted silicon on insulator (FD-SOI) process, has a 10 MHz RF bandwidth (BW) centered around 2.5 GHz and occupies an area of 0.14 mm ² while consuming 10.1 mW. Its measured double-sideband (DSB) noise figure (NF) is 20.5 dB, and its out-of-band (OOB) input intercept point 3 (IIP3) and B1dB are +16 and −0.3 dBm, respectively.