A novel method for SEE validation of complex SoCs using Low-Energy Proton beams

G. Furano, S. Di Mascio, T. Szewczyk, A. Menicucci, L. Campajola, F. Di Capua, A. Fabbri, M. Ottavi

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

7 Citations (Scopus)

Abstract

This paper discusses radiation tests on complex System-on-Chip (SoC) controllers using Low-Energy Protons (LEPs). The aim of this novel set of guidelines is to be also applicable to System In Package (SIP) or hybrid components that are now often used to overcome printed circuit board's real estate restrictions in Hi-Rel electronics. Despite the growing success of microcontrollers SoC in HiRel applications, general and standardized methods for Single Event Effects (SEE) testing of complex SoCs have not been widely established. This paper will propose a general methodology, structured in a modular test sequence for test definition, coding, validation and setup, with suggestions relevant also for FPGA tests and potentially for system-level characterization of miniaturized assemblies. It will be illustrated by the relevant example of a microcontroller solution including lockstep options. Our methodology proposes using a first step with LEPs for irradiation, and this paper compares this approach with current techniques and standards, showing how proton testing is becoming increasingly interesting, especially for ultra-deep submicron processes in proton dominated environments like thin-shielded Low Earth Orbit (LEO) missions or aircraft avionics. The proposed method can be used for testing a wide variety of SoCs, providing a good trade-off between a rigorous and expensive space qualification process and the usage of an untested COTS or non fault tolerant IPs with unpredictable failure modes. LEP tests have a high risk of misinterpretation, and a correct guideline is paramount to exploit their value.
Original languageEnglish
Title of host publication2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016
DOIs
Publication statusPublished - 2016
Externally publishedYes
Event2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016 - University of Connecticut, Storrs, United States
Duration: 19 Sept 201620 Sept 2016

Conference

Conference2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016
Abbreviated titleDFT
Country/TerritoryUnited States
CityStorrs
Period19/09/1620/09/16

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