A PLL Exploiting Sub-Sampling of the VCO Output to Reduce In-band Phase Noise

X. Gao, Eric A.M. Klumperink, Mounir Boshali, Bram Nauta

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    Abstract— In this paper, we present a 2.2-GHz low jitter PLL based on sub-sampling. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N2 in this sub-sampling PLL. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. A frequency locked loop guarantees correct frequency locking without degenerating jitter performance. The PLL implemented in a standard 0.18-μm CMOS process consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 × 0.45 mm2. The in-band phase noise at 200 kHz offset is measured to be -126 dBc/Hz and the rms PLL output jitter integrated from 10 kHz to 40 MHz is 0.15 ps.
    Original languageUndefined
    Title of host publicationProceedings of the 20th Annual Workshop on Circuits, Systems and Signal Processing
    Place of PublicationUtrecht
    Number of pages4
    ISBN (Print)978-90-73461-62-8
    Publication statusPublished - 26 Nov 2009
    Event20th Annual Workshop on circuits, Systems and Signal Processing, Prorisc 2009 - Veldhoven, Netherlands
    Duration: 26 Nov 200927 Nov 2009
    Conference number: 20

    Publication series



    Conference20th Annual Workshop on circuits, Systems and Signal Processing, Prorisc 2009


    • METIS-264519
    • EWI-17365
    • IR-69785

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