A reconfigurable architecture for the phylogenetic likelihood function

Nikolaos Alachiotis*, Alexandros Stamatakis, Euripides Sotiriades, Apostolos Dollas

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

16 Citations (Scopus)

Abstract

As FPGA devices become larger, more coarse-grain modules coupled with large scale reconfigurable fabric become available, thus enabling new classes of applications to run efficiently, as compared to a general-purpose computer. This paper presents an architecture that benefits from the large number of DSP modules in Xilinx technology to implement massive floating point arithmetic. Our architecture computes the Phylogenetic Likelihood Function (PLF) which accounts for approximately 95% of total execution time in all state-of-the-art Maximum Likelihood (ML) based programs for reconstruction of evolutionary relationships. We validate and assess performance of our architecture against a highly optimized and parallelized software implementation of the PLF that is based on RAxML, which is considered to be one of the fastest and most accurate programs for phylogenetic inference. Both software and hardware implementations use double precision floating point arithmetic. The new architecture achieves speedups ranging from 1.6 up to 7.2 compared to a high-end 8-way dual-core general-purpose computer running the aforementioned highly optimized OpenMP-based multi-threaded version of the PLF.

Original languageEnglish
Title of host publication2009 International Conference on Field Programmable Logic and Applications, FPL 2009
Place of PublicationPiscataway, NJ
PublisherIEEE
Pages674-678
Number of pages5
ISBN (Electronic)978-1-4244-3892-1
DOIs
Publication statusPublished - 2009
Externally publishedYes
Event19th International Conference on Field Programmable Logic and Applications, FPL 2009 - Prague, Czech Republic
Duration: 31 Aug 20092 Sept 2009
Conference number: 19

Publication series

NameInternational Conference on Field Programmable Logic and Applications (FPL)
PublisherIEEE
Volume2009
ISSN (Print)1946-147X
ISSN (Electronic)1946-1488

Conference

Conference19th International Conference on Field Programmable Logic and Applications, FPL 2009
Abbreviated titleFPL
Country/TerritoryCzech Republic
CityPrague
Period31/08/092/09/09

Fingerprint

Dive into the research topics of 'A reconfigurable architecture for the phylogenetic likelihood function'. Together they form a unique fingerprint.

Cite this