With the advance of semiconductor technology, global on-chip wiring is becoming a limiting factor for the overall performance of large System-on-Chip (SoC) designs. In this thesis we propose a global communication architecture that avoids this limitation by structuring and shortening of the global wires. The communication architecture is used in a multiprocessor SoC for streaming DSP applications. The SoC is intended as a platform for wireless multimedia devices, such as PDAs, mobile phones, mobile medical systems, car infotainment systems, etc. To improve the performance of the communication in our SoC we use a Network-on-Chip (NoC) architecture. A NoC provides the chip with a high-performance global communication infrastructure, at the same time structures the global on-chip wires and makes their electrical parameters predictable and controllable. By contrast, the bus solutions and the ad-hoc communications solutions used till now in SoC designs result in long wires with unpredictable electrical parameters and require costly design iterations for improving the communication performance. Our specific NoC uses virtual channel flow control and source routing to provide guaranteed communication services, as well as best effort services. Our NoC is the first on-chip network designed for a run-time reconfigurable system. It offers fast reconfiguration and requires low configuration overhead. Configuring a network path takes less than a millisecond and only costs a few bytes of data overhead. Such time and data overhead is affordable by the run-time reconfigurable SoC for the class of streaming applications we consider. Our NoC is particularly suitable for the specific traffic conditions created by streaming DSP applications. These applications have a simple structure and create simple traffic patterns but need a high data throughput. The main part of the traffic consists of data streams that require guaranteed services. However, our NoC also supports the small part of the traffic with fine granularity and irregular behaviour that requires only best effort services. The implementation area of our network router in 0.13 ï¿½?ï¿½m technology can be as small as 0.05 mm2 depending on the network design parameters. A network channel throughput of several Gbit/s can be achieved, which is enough to satisfy the system applications demands. The specific contributions of this thesis are: 1.We propose a NoC architecture for a run-time reconfigurable multiprocessor SoC that supports streaming DSP applications. To the best of our knowledge, this is the first NoC targeted at a run-time reconfigurable SoC. 2.We propose an architecture of a virtual channel router, which in contrast to conventional architectures is able to provide predictable communication services and has a lower implementation area cost than conventional architectures. 3.The predictable performance of our network simplifies the mapping of streaming DSP applications to our multiprocessor system. System reconfiguration can be done in linear time avoiding the NP-complete solutions common for statically scheduled real-time systems. Thanks to this linearity, system reconfiguration can be done at run-time.
|Award date||31 Jan 2007|
|Place of Publication||Enschede|
|Publication status||Published - 31 Jan 2007|